
24
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map)
CHAPTER
5 PERIPHERAL CIRCUITS AND OPERATION
The peripheral circuits of the S1C88409 are interfaced with the CPU in the memory mapped I/O method.
Thus, the peripheral circuits can be controlled by using the memory operation instructions to access the
I/O memory. This chapter explains the operation and control of the peripheral circuits, individually.
5.1 I/O Memory Map
Table 5.1.1(a) I/O Memory map (00FF00H, 00FF01H)
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF00
MCU
mode
Bus mode (CPU mode) selection
Expanded 64K chip enable mode
–
CE2(R32)
CE signal output enable/disable
CE1(R31)
enable: CE signal output
CE0(R30)
disable: DC output (R3x)
R/W
–
R/W
0
1
–
1
–
CE2 disable
CE1 disable
CE0 disable
–
CE2 enable
CE1 enable
CE0 enable
Only for 64K bus
mode
"0" when being read
In the single chip
mode, these setting
are fixed at DC output
BSMD1
BSMD0
CEMD1
CEMD0
–
CE2
CE1
CE0
D7
D6
D5
D4
D3
D2
D1
D0
BSMD1
1
0
BSMD0
1
0
1
0
Mode
4M(Maximum)
4M(Minimum)
64K
Single chip
CEMD1
1
0
CEMD0
1
0
1
0
Mode
–
32K(CE0)
16K(CE0, CE1)
8K(CE0–CE2)
00FF00
MPU
mode
Bus mode (CPU mode) selection
Expanded 64K chip enable mode
–
CE2(R32)
CE signal output enable/disable
CE1(R31)
enable: CE signal output
CE0(R30)
disable: DC output (R3x)
R/W
–
R/W
1
–
1
–
CE2 disable
CE1 disable
CE0 disable
–
CE2 enable
CE1 enable
CE0 enable
Initial setting can be
selected from 3 types
(64K, 4M min, 4M
max) by mask option
Only for 64K bus
mode
"0" when being read
BSMD1
BSMD0
CEMD1
CEMD0
–
CE2
CE1
CE0
D7
D6
D5
D4
D3
D2
D1
D0
BSMD1
1
0
BSMD0
1
0
1
0
Mode
4M(Maximum)
4M(Minimum)
64K
Option selection
CEMD1
1
0
CEMD0
1
0
1
0
Mode
64K(CE0)
32K(CE0, CE1)
16K(CE0–CE2)
8K(CE0–CE2)
00FF01
–
Wait state control
CPU operating clock switch
OSC3 oscillation ON/OFF control
VD1 output level setting
–
R/W
–
0
–
OSC1
Off
–
OSC3
On
"0" when being read
–
WT1
WT0
CLKCHG
OSCC
VD1C1
VD1C0
D7
D6
D5
D4
D3
D2
D1
D0
WT1
1
0
WT0
1
0
1
0
Number of states
12(3 cycles)
8(2 cycles)
4(1 cycle)
No wait
VD1C1
1
0
VD1C0
1
0
1
0
VD1 (Typ.)
4.2 V
3.2 V
1.6 V
2.4 V
Note: All the interrupts including NMI are masked until the appropriate values are written to both the
"00FF00H" and "00FF01H" addresses.