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EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
FCTM32: Clock timer 32 Hz interrupt factor flag
(00FF29HD3)
FCTM8: Clock timer 8 Hz interrupt factor flag
(00FF29HD4)
FCTM2: Clock timer 2 Hz interrupt factor flag
(00FF29HD5)
FCTM1: Clock timer 1 Hz interrupt factor flag
(00FF29HD6)
FT60S: Clock timer 60S interrupt factor flag
(00FF29HD7)
Indicates the generation of clock timer interrupt
factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FCTM32, FCTM8, FCTM2 and FCTM1 are the
interrupt factor flags corresponding to the 32 Hz, 8
Hz, 2 Hz and 1 Hz interrupt, and are set to "1" at
the falling edge of the respective signals. FT60S is
the interrupt factor flag corresponding to the 60S
interrupt and is set to "1" due to an overflow of the
60-second counter.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
At initial reset, the interrupt factor flags are all
reset to "0".
5.11.4 Programming notes
(1) The clock timer actually entqzs into RUN or
STOP status at the falling edge of the 256 Hz
signal after writing to the TMRUN register.
Consequently, when "0" is written to TMRUN,
the timer stops after counting once more (+1).
TMRUN is read as "1" until the timer actually
stops.
Figure 5.11.4.1 shows the timing chart at the
RUN/STOP control.
TMRUN (WR)
TMDX
57H
58H 59H 5AH 5BH
5CH
TMRUN (RD)
256 Hz
Fig. 5.11.4.1 Timing chart at RUN/STOP control
(2) The 60-second counter is preset only when data
is written to the TMMD register. The register
does not maintain the preset data and returns
to 0-second when the counter overflows.
To prevent the counter from abnormal opera-
tion, do not preset data without a range of 0 to
59 (BCD).