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參數資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數： | 53/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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136
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
5.14.6 Receive error
During receiving the following three kinds of
errors can be detected by an interrupt.
Parity error
When the EPR register has been set to "1" (with
parity), a parity check is executing during receiv-
ing (except for the clock synchronous mode).
The parity check is done when data received in the
shift register is transferred to the receive data
buffer. It checks matching with the receive data
and the setting of the PMD register (odd parity or
even parity). If they are not matched, it is recog-
nized as a parity error and the parity error flag
PER and the error interrupt factor flag FSERR are
set to "1". An error interrupt is generated at this
point when the interrupt has been enabled.
The PER flag is reset to "0" by writing "1".
The received data is transferred to the receive data
buffer even when a parity error has generated, and
the receiving operation also continues. However,
the received data cannot be assured.
Framing error
When the serial interface receives a stop bit as "0",
it judges that the synchronization is deviated and
generates a framing error.
When a framing error is generated, the framing
error flag FER and the error interrupt factor flag
FSERR are set to "1". An error interrupt is gener-
ated at this point when the interrupt has been
enabled.
The FER flag is reset to "0" by writing "1".
The received data is transferred to the receive data
buffer even when a framing error has generated,
and the receiving operation also continues.
However, even when the following data receiving
does not generate a framing error, the data cannot
be assured.
Overrun error
In the asynchronous mode, an overrun error
occurs when the next data is received before
writing "1" to RXTRG.
In the clock synchronous slave mode, an overrun
error occurs when the next data is received before
reading the received data.
When an overrun error is generated, the overrun
error flag OER and the error interrupt factor flag
FSERR are set to "1". An error interrupt is gener-
ated at this point when the interrupt has been
enabled.
The OER flag is reset to "0" by writing "1".
The received data is transferred to the receive data
buffer even when an overrun error has generated,
and the receiving operation also continues.
Furthermore, when the received data is transferred
to the receive data buffer at the same time "1" is
written to RXTRG in the asynchronous mode, it is
recognized as an overrun error.
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