
S1C88409 TECHNICAL MANUAL
EPSON
51
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
5.3 Watchdog Timer
5.3.1 Configuration of watchdog timer
The S1C88409 has a built-in watchdog timer that detects CPU runaway.
OSC1
oscillation circuit
Clock
selector
1/16
divider
WDCL
Watchdog timer
(12 bits)
WDRST
EWD
fOSC1
OSC3
oscillation circuit
1/16
divider
fOSC3
Overflow
Non-maskable
interrupt (NMI)
Fig. 5.3.1.1 Block diagram of watchdog timer
The watchdog timer is composed of a 12-bit up-
counter that uses the OSC1 or OSC3 oscillation
circuit as a clock source. This counter must be reset
cyclically by software. If the counter is not reset
and an overflow occurs, the watchdog timer
generates NMI (non-maskable interrupt) to the
CPU.
Figure 5.3.1.1 is a block diagram of the watchdog
timer.
5.3.2 Control of watchdog timer
Input clock selection
The input clock of the watchdog timer can be
selected using the input clock selection register
WDCL from the two listed below.
WDCL = "1": 1/16 OSC1 dividing clock
WDCL = "0": 1/16 OSC3 dividing clock
At initial reset, the input clock is set to fOSC1/16.
The following shows an example of a watchdog
timer reset cycle according to the input clock
selected.
When fOSC1/16 is selected:
fOSC1 = 32.768 kHz within 2 sec
When fOSC3/16 is selected:
fOSC3 = 1 MHz
within 64 msec
fOSC3 = 6 MHz
within 10 msec
fOSC3 = 8 MHz
within 8 msec
The WDCL register is set to write disabling status
usually to prevent modification of the reset cycle
by a wrong writing. To change the input clock, it is
necessary to set the WDCL register in write
authorized status by writing "1" to the write enable
register WRWD beforehand. The write authoriza-
tion by the WRWD register enables only one write
for the WDCL register. When data is written to the
WDCL register after setting in write authorization,
the WRWD register returns to "0", and the WDCL
register is also returned to write disabling status.
Resetting the watchdog timer
When the watchdog timer is used, it is necessary
to reset the counter before an overflow is gener-
ated. The watchdog timer is reset by writing "1" to
the watchdog timer reset bit WDRST.
By resetting the watchdog timer on the main
routine, program runaway that does not pass the
reset routine can be detected. Ordinarily this
routine is incorporated to a place where it is
executed regularly.
Operation in HALT/SLEEP status
(1) HALT status
The OSC1 oscillation circuit and the OSC3
oscillation circuit operate in HALT status.
Therefore, the watchdog timer also operates.
The watchdog timer generates NMI when
HALT status continues more than a reset cycle.
HALT status is released at that point.
(2) SLEEP status
The OSC1 oscillation circuit and the OSC3
oscillation circuit stop in SLEEP status. There-
fore, the watchdog timer also stops. Since the
counter maintains the value at the point it
stops, the counter resumes counting from the
value after SLEEP status is canceled. However,
the oscillation clock becomes unstable immedi-
ately after SLEEP is canceled. Therefore, reset
the watchdog timer before shifting to SLEEP
status and after SLEEP status is canceled so
that an unnecessary NMI will not be generated.