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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 127/250頁(yè) |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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202
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 6: SUMMARY OF NOTES
6.3 Precautions on Mounting
<Oscillation Circuit>
q Oscillation characteristics change depending
on conditions (board pattern, components
used, etc.).
In particular, when a ceramic oscillator or
crystal oscillator is used, use the oscillator
manufacturer's recommended values for
constants such as capacitance and resistance.
q Disturbances of the oscillation clock due to
noise may cause a malfunction. Consider the
following points to prevent this:
(1) Components which are connected to the
OSC1, OSC2, OSC3, OSC4 terminals, such
as oscillators, resistors and capacitors,
should be connected in the shortest line.
(2) As shown in the right hand figure, make a
VSS pattern as large as possible at circum-
scription of the OSC1, OSC2, OSC3, OSC4
terminals and the components connected to
these terminals.
Furthermore, do not use this VSS pattern for
any purpose other than the oscillation
system.
OSC4
OSC3
VSS
Sample VSS pattern
(3) When supplying an external clock to the
OSC1 (OSC3) terminal, the clock source
should be connected to the OSC1 (OSC3)
terminal in the shortest line.
Furthermore, do not connect anything else
to the OSC2 (OSC4) terminal.
q In order to prevent unstable operation of the
oscillation circuit due to current leak between
OSC3 and VDD, please keep enough distance
between OSC3 and VDD or other signals on the
board pattern.
<Reset Circuit>
q The power-on reset signal which is input to the
RESET terminal changes depending on condi-
tions (power rise time, components used, board
pattern, etc.).
Decide the time constant of the capacitor and
resistor after enough tests have been completed
with the application product.
When the built-in pull-up resistor is added to
the RESET terminal by mask option, take into
consideration dispersion of the resistance for
setting the constant.
q In order to prevent any occurrences of unneces-
sary resetting caused by noise during operat-
ing, components such as capacitors and
resistors should be connected to the RESET
terminal in the shortest line.
<Power Supply Circuit>
q Sudden power supply variation due to noise
may cause malfunction. Consider the following
points to prevent this:
(1) The power supply should be connected to the
VDD, VSS, AVDD, AVSS and AGND, AVREF
terminals with patterns as short and large as
possible.
In particular, the power supply for AVDD, AVSS,
AGND and AVREF affects A/D conversion and
D/A conversion accuracy.
(2) When connecting between the VDD and VSS
terminals with a bypass capacitor, the terminals
should be connected as short as possible.
VDD
VSS
Bypass capacitor connection example
VDD
VSS
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