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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 55/250頁 |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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138
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Transmit completion interrupt
This interrupt factor occurs when the transmission
of the data written in the shift register has com-
pleted, and sets the interrupt factor flag FSTX to
"1". It generates an interrupt to the CPU when the
interrupt enable register ESTX has been set to "1"
and the interrupt priority register PSI has been set
to a higher level than the setting of the interrupt
flag (I0, I1).
When the interrupt is disabled by setting the ESTX
register to "0", interrupt does not occur to the CPU.
However, even in this case the FSTX flag is set to
"1".
The interrupt factor flag FSTX is reset to "0" by
writing "1".
After the interrupt factor occurs, it is possible to
write the next transmission data and to start the
transmission (writing "1" to TXTRG).
The exception processing vector addresses for the
transmit completion interrupt are set as follows:
Transmit completion interrupt: 00001EH
Receive completion interrupt
This interrupt factor occurs when the data received
into the shift register is transferred to the receive
data buffer after receiving is completed, and sets
the interrupt factor flag FSRX to "1". It generates
an interrupt to the CPU when the interrupt enable
register ESRX has been set to "1" and the interrupt
priority register PSI has been set to a higher level
than the setting of the interrupt flag (I0, I1).
When the interrupt is disabled by setting the ESRX
register to "0", interrupt does not occur to the CPU.
However, even in this case the FSRX flag is set to
"1".
The interrupt factor flag FSRX is reset to "0" by
writing "1".
After the interrupt factor occurs, it is possible to
read the received data.
The interrupt factor flag FSRX is set to "1" even
when a parity error or a framing error has oc-
curred.
The exception processing vector addresses for the
receive completion interrupt are set as follows:
Receive completion interrupt: 00001CH
Receive error interrupt
This interrupt factor occurs when a parity error , a
framing error or an overrun error is detected
during receiving, and sets the interrupt factor flag
FSERR to "1" at the same point of the receive
completion interrupt generation. It generates an
interrupt to the CPU when the interrupt enable
register ESERR has been set to "1" and the inter-
rupt priority register PSI has been set to a higher
level than the setting of the interrupt flag (I0, I1).
When the interrupt is disabled by setting the
ESERR register to "0", interrupt does not occur to
the CPU. However, even in this case the FSERR
flag is set to "1".
The interrupt factor flag FSERR is reset to "0" by
writing "1".
Since all three kinds of errors result in the same
interrupt factor, the error generated should be
distinguished using the error flags PER (parity
error), OER (overrun error) and FER (framing
error).
The exception processing vector addresses for the
receive error interrupt are set as follows:
Receive error interrupt: 00001AH
Note: When a parity error or a framing error
occurs, both the receive error interrupt
factor flag FSERR and the receive comple-
tion interrupt factor flag FSRX are simulta-
neously set to "1". However, since the
receive error interrupt has priority over the
receive completion interrupt, the receive
error interrupt process is executed first.
Therefore, it is necessary to reset the FSRX
flag in the receive error handling routine.
When a receive error interrupt occurs due
to an overrun, receive completion interrupt
does not occur.
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