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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 121/250頁(yè) |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
197
CHAPTER 6: SUMMARY OF NOTES
CHAPTER
6SUMMARY OF NOTES
6.1 Notes for Low Current Consumption
The S1C88409 can turn circuits, which consume a large amount of power, ON or OFF by the control
registers.
These control registers lower the current consumption through programs that operate the circuits at the
minimum levels. Table 6.1.1 shows the circuits and the control registers (instructions).
Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS" for the current consumption.
Table 6.1.1 Circuits and control registers
Circuit
CPU
Oscillation circuit
Operating voltage VD1
SVD circuit
A/D converter
D/A converter
Touch panel controller
Status at initial reset
HALT and SLP instructions
CLKCHG, OSCC
VD1C
SVDON
ADRUN
DAE
RST
Control register/instruction
Operating
OSC1 clock (CLKCHG="0")
OSC3 oscillation OFF (OSCC="0")
2.4 V (VD1C="00B")
OFF status (SVDON="0")
OFF status (ADRUN="0")
OFF status (DAE="0")
OFF status (RST="0")
6.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
System controller and bus control
After initial reset, all the interrupts including NMI
are masked until the appropriate values are
written to the I/O memory addresses "00FF00H"
and "00FF01H" to prevent malfunctions that may
occur before setting the system configuration.
Therefore, write data to the addresses in the initial
routine even though the initial settings are used.
Furthermore, set the stack pointer SP prior to
writing so that interrupt processing will operate
normally.
Watchdog timer
(1) When the watchdog timer NMI is authorized,
it is necessary to reset the counter by software
before an overflow is generated.
(2) At initial reset, the watchdog timer starts
counting by inputting the fOSC1/16 clock and is
set to generate NMI. When the watchdog timer
is not used, write "0" to the EWD register
before the first overflow is generated.
(3) The count operation is continued even when
the EWD register is set to "0" if the clock is
input. Therefore, when NMI is invalidated
temporarily, reset the watchdog timer before
changing back the EWD register to "1".
(4) The oscillation clock becomes unstable imme-
diately after SLEEP is canceled. Therefore, reset
the watchdog timer before shifting to SLEEP
status and after SLEEP status is canceled so
that an unnecessary NMI will not be generated.
Oscillation circuit
(1) The VD1 level must be switched while the
OSC3 oscillation circuit is off (before turning
on and after turning off). Switching during
operation may cause malfunction.
Furthermore, the VD1 voltage required at least
5 msec of voltage stabilizing time after switch-
ing. Do not turn the OSC3 oscillation circuit on
during this period.
(2) VD1 cannot be switched directly to a level that
is two or three levels different from the current
level. The middle level must be set between the
switching.
To switch from 1,6 (3.2) V to 3.2 (1.6) V:
1.6 V
→ 2.4 V → 3.2 V
1.6 V
← 2.4 V ← 3.2 V
To switch from 1.6 (4.2) V to 4.2 (1.6) V:
1.6 V
→ 2.4 V → 3.2 V → 4.2 V
1.6 V
← 2.4 V ← 3.2 V ← 4.2 V
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