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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 61/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
143
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Asynchronous mode
(1) Transmission timing in asynchronous mode
Figure 5.14.9.5 shows the transmission timing
of the 8-bit asynchronous mode (stop bit = 2
bits, with parity).
After writing "1" to the TXTRG bit, each bit of
transmission data is output from the SOUT
terminal at the falling edge of the sampling clock
generated internally. When the last bit is output, a
transmit completion interrupt is generated at the
rising edge of the clock. The sampling clock is
generated by dividing the 8-bit programmable
timer output in 1/16. (See Figure 5.14.4.3.)
(2) Receiving timing in asynchronous mode
Figure 5.14.9.6 shows the receiving timing of
the 8-bit asynchronous mode (stop bit = 1 bit,
with parity).
When a start bit is input from the SIN terminal, a
sampling clock for data receiving is generated
(see Figure 4.14.4.2). The status of the SIN
terminal is input at each rising edge of the
sampling clock. When the last stop bit is input, a
receive completion interrupt is generated simulta-
neously. After the interrupt is generated, the
received data can be read from the TRXD register.
When a parity error or a framing error (stop bit =
"0") occurs, the error interrupt is generated at the
same time as the receive completion interrupt.
When receiving data in the asynchronous
mode, it is necessary to write "1" to the RXTRG
bit after reading received data. An internal
signal OERCS checks overrun error. It goes "1"
at the end of every data receiving (immediately
after inputting the stop bit), and goes "0" by
writing "1" to the RXTRG bit. An overrun error
occurs if the OERCS signal has not returned to
"0" when the stop bit is input. In this case, the
error interrupt is generated at the same time as
the receive completion interrupt. When the
received data is transferred to the receive data
buffer at the same time "1" is written to
RXTRG, it is recognized as an overrun error.
Pay attention to the write timing.
Note: When a parity error or a framing error
occurs, both the receive error interrupt
factor flag FSERR and the receive comple-
tion interrupt factor flag FSRX are simulta-
neously set to "1". However, since the
receive error interrupt has priority over the
receive completion interrupt, the receive
error interrupt process is executed first.
Therefore, it is necessary to reset the FSRX
flag in the receive error handling routine.
When a receive error interrupt occurs due
to an overrun, receive completion interrupt
does not occur.
Fig. 5.14.9.5 Transmission timing (8-bit asynchronous mode, stop bit = 2 bits, with parity)
Fig. 5.14.9.6 Receiving timing (8-bit asynchronous mode, stop bit = 1 bit, with parity)
TXEN
TXTRG (WR)
Sampling clock
SOUT
TXTRG (RD)
s1: start bit, s2 & s3: stop bit, p: parity bit
Transmit completion
interrupt generation
s1
D0
D1
D2
D3
D4
D5
D6
D7
p
s2
s3
RXEN
RXTRG (WR)
Sampling clock
SIN
TRXD (RD)
RXTRG (RD)
OERCS
OER
start bit
stop bit
parity bit
s1:
s2:
p:
s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2
Receive completion
interrupt generation
Overrun error
interrupt generation
Receive completion
interrupt generation
Interrupt is generated
when parity error or
framing error is detected
Interrupt is generated
when parity error or
framing error is detected
1st data
2nd data
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