
S1C88409 TECHNICAL MANUAL
EPSON
53
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
WDCL: Input clock selection register
(00FF53HD5)
Selects the input clock for the watchdog timer.
When "1" is written: fOSC3/16
When "0" is written: fOSC1/16
Reading: Valid
When "1" is written to the WDCL register, fOSC3/16
clock is input to the watchdog timer as the count
clock. When "0" is written, fOSC1/16 clock is input.
When fOSC3/16 clock is used, the watchdog timer
stops if the OSC3 oscillation circuit stops (includ-
ing SLEEP). In this case, the counter value at stop
is maintained.
Writing to the WDCL register is effective only
when the WRWD register is set to "1".
At initial reset, the WDCL register is set to "0"
(fOSC1/16).
WDRST: Watchdog timer reset (00FF53HD0)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" to WDRST, the watchdog timer is
reset and restarts immediately after. When "0" is
written, no operation results.
WDRST is dedicated for writing, and is always "0"
for reading.
5.3.5 Programming notes
(1) When the watchdog timer NMI is authorized,
it is necessary to reset the counter by software
before an overflow is generated.
(2) At initial reset, the watchdog timer starts
counting by inputting the fOSC1/16 clock and is
set to generate NMI. When the watchdog timer
is not used, write "0" to the EWD register
before the first overflow is generated.
(3) The count operation is continued even when
the EWD register is set to "0" if the clock is
input. Therefore, when NMI is invalidated
temporarily, reset the watchdog timer before
changing back the EWD register to "1".
(4) The oscillation clock becomes unstable imme-
diately after SLEEP is canceled. Therefore, reset
the watchdog timer before shifting to SLEEP
status and after SLEEP status is canceled so
that an unnecessary NMI will not be generated.