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EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.3 System Configuration
System configuration of the S1C88409 is classified
in 2 types according to use.
1) Single-chip system
2) Multi-chip system
To construct these systems, the S1C88409 has been
designed to switch the bus mode (configuration of
the external bus) by software and/or mask option.
1.3.1 Single-chip system
The single-chip system has the smallest configura-
tion that uses the S1C88409 as the CPU of the
system and does not expand any memory and
devices outside. It is suitable for various controller
systems.
Since it does not use an external bus, the bus mode
of the S1C88409 should be set to the MCU/ single-
chip mode (see Section 3.5). (Initial setting)
The memory that can be used is limited to the
built-in area.
ROM ...8KB
RAM ...3.75KB (display memory is included)
The I/O ports shared with the external bus can be
used entirely as general-purpose I/O ports.
I/O
IN
OUT
S1C88409
Fig. 1.3.1.1 Configuration of single-chip system
1.3.2 Multi-chip system
With the S1C88409 as the CPU, the multi-chip
system has expanded memory as well as other
expanded devices. It covers a wide range of
applications. Memory and devices are connected
to the external bus of the S1C88409 and are all
controlled by the S1C88409.
The bus mode of the S1C88409 can be set to the
expanded mode (see Section 3.5) according to scale
of the system.
MCU or MPU*/Expanded 64K mode
For systems with 64KB or less expanded
memory
MCU or MPU*/Expanded 4M minimum mode
For systems with 64KB to 12MB (4M
× 3)
expanded memory (However, program
memory is 64KB or less)
MCU or MPU*/Expanded 4M maximum mode
For systems with 64KB to 12MB (4M
× 3)
expanded memory (For systems that require
64KB or more program memory)
The MCU mode is set when the internal ROM
is used, and the MPU mode is set when the
internal ROM is not used.
Refer to Section 3.6, "External Bus", for the bus
configuration.
S1C88409
External
Device
Address bus (A0–A21)
Data bus (D0–D7)
RD
WR
CE0
CE1
CE2
External
Device
External
Device
I/O
Fig. 1.3.2.1 Configuration of multi-chip system