參數(shù)資料
型號(hào)： S1C88409D
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 210/250頁(yè)
文件大小： 1877K
代理商： S1C88409D
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52
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
When watchdog timer is not used
The watchdog timer always operates unless the
oscillation circuit specified for the input clock
stops. If monitoring the system by the watchdog
timer is unnecessary, it is possible to disable the
watchdog timer interrupt (NMI) by writing "0" to
the watchdog timer enable register EWD.
At initial reset, the watchdog timer starts counting
by inputting the fOSC1/16 clock and is set to
generate NMI. When the watchdog timer is not
used, write "0" to the EWD register before the first
overflow is generated.
The EWD register is set to write disabling status
same as the WDCL register. Set it in write autho-
rized status using the WRWD register before
writing to the EWD register. In this case, only one
write is enabled for the EWD register.
5.3.3 Interrupt function
When the watchdog timer is not reset cyclically by
software, the watchdog timer outputs an interrupt
signal to the NMI (level 4) input of the core CPU.
This interrupt cannot be masked and the exception
processing has priority over other interrupts.
Refer to the "S1C88 Core CPU Manual" for details
of the NMI exception processing.
This exception processing vector address is set to
000004H.
When the EWD register is set to "0", this interrupt
is not generated.
5.3.4 I/O memory of watchdog timer
Table 5.3.4.1 shows the control bits for the watch-
dog timer.
Table 5.3.4.1 Watchdog timer control bits
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF53
EWD, WDCL write enable
Watchdog timer NMI enable
Watchdog timer input clock selection
–
Watchdog timer reset
R/W
–
W
0
1
0
–
Write disable
NMI disable
fOSC1/16
–
Invalid
Write enable
NMI enable
fOSC3/16
–
Reset
1
"0" when being read
WRWD
EWD
WDCL
–
WDRST
D7
D6
D5
D4
D3
D2
D1
D0
1 Writing to EWD or WDCL is valid after "1" is written to WRWD. WRWD is automatically returns to "0" after writing to EWD or WDCL.
WRWD: EWD, WDCL write enable register
(00FF53HD7)
Enables writing to the EWD and WDCL register.
When "1" is written: Write is enabled
When "0" is written: Write is disabled
Reading: Valid
The EWD and WDCL registers are set to write
disabling status usually to prevent unnecessary
modification. When "1" is written to the WRWD
register, only one write is permitted. When data is
written to either the EWD or WDCL registers or
both, the WRWD register returns to "0", and the
EWD and WDCL registers go to write disabling
status.
Writing "0" to the WRWD register during a write
authorized state (WRWD="1") also returns to write
disabling status.
At initial reset, the WRWD register is set to "0"
(write is disabled).
EWD: NMI enable register
(00FF53HD6)
Controls non-maskable interrupt (NMI) generation
by watchdog timer.
When "1" is written: NMI is valid
When "0" is written: NMI is invalid
Reading: Valid
When "0" is written to the EWD register, the
watchdog timer interrupt signal is masked and
NMI is not generated to the CPU. When the EWD
register is set to "1", NMI is generated due to an
overflow of the counter.
Writing to the EWD register is effective only when
the WRWD register is set to "1".
The count operation is continued even when the
EWD register is set to "0" if the clock is input.
Therefore, when NMI is invalidated temporarily,
reset the watchdog timer before changing back the
EWD register to "1".
At initial reset, the EWD register is set to "1" (NMI
is valid).
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