
14
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 3: CPU AND MEMORY
Table 3.3.1 Correspondence between vector addresses and exception processing factors
Vector address
000000H
000002H
000004H
000006H
000008H
00000AH
00000CH
00000EH
000010H
000012H
000014H
000016H
000018H
00001AH
00001CH
00001EH
000020H
000022H
000024H
000026H
000028H
000032H
000034H
↓
0000FEH
Symbol
RESET
ZDIV
NMI
IRK10
IRK11
IRK12
IRK13
IRK0
IRTU0
IRTC0
IRTU1
IRTC1
IRTU2
IRSER
IRSRX
IRSTX
IRTP1
IRTP2
IRLCD
IRAD
IRRTC
–
Priority
High
↑
↓
Low
No
Priority
rating
Exception processing factor
Reset
Zero division
NMI (Watchdog timer)
Input port K1
Input port K0
16-bit programmable timer 0
16-bit programmable timer 1
8-bit programmable timer
Serial interface
Touch panel controller
LCD controller
A/D converter
Clock timer
System reserved (cannot be used)
Software interrupt
K10 input interrupt
K11 input interrup
K12 input interrup
K13 input interrup
K00–K07 input interrup
Underflow interrupt
Compare match interrupt
Underflow interrupt
Compare match interrupt
Underflow interrupt
Receive error interrupt
Receive completion interrupt
Receive error interrupt
Pen-down interrupt
Converted data update interrupt
Data transfer completion interrupt
A/D conversion completion interrupt
32Hz/8Hz/2Hz/1Hz/60S interrupt
3.3 Exception Processing Vectors
In the S1C88409, 000000H–000029H in the program
area are assigned as exception processing vectors.
Furthermore, from 000034H to 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 shows the correspondence between the
vector addresses and the exception processing
factors.
The start address of the exception processing
routine should be written to the respective vector
address and the next address in order of low and
high-order start address. When an exception
processing factor is generated, the exception
processing routine which starts from the recorded
address is executed.
When multiple exception processing factors are
generated at the same time, the exception process-
ing is executed according to priority.
The priority of interrupts shown in Table 3.3.1
assumes that the interrupt priority levels are all
the same. The interrupt priority levels can be set
by software in each interrupt system. (See Section
5.20, "Interrupt and Standby Mode".)
Note: The exception processing not including
reset saves the SC (system condition flag)
and PC (program counter) to the stack
before branching to the exception process-
ing routine. Consequently, when returning
to the main routine from exception process-
ing routines, use the RETE instruction.
Refer to the "S1C88 Core CPU Manual" for CPU
operation when an exception processing factor is
generated.
3.4 CC (Customized Condition Flag)
The S1C88409 does not use the customized
condition flag (CC) in the core CPU. Accordingly,
it cannot be used as a branching condition for the
conditional branching instruction (JRS, CARS).
3.5 Chip Mode
3.5.1 MCU mode and MPU mode
The S1C88409 is set in two chip operating mode by
the MCU/MPU terminal.