
66
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit)
PK11ON: EXCL01 clock control register
(00FF15HD1)
Controls the event counter clock of the 16-bit
programmable timer 1.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
By writing "1" to the PK11ON register, the EXCL01
(K11 input) clock is output to the 16-bit program-
mable timer 1.
When "0" is written, the clock is not output.
At initial reset, the PK11ON register is set to "0"
(OFF).
PST20–PST22: 8-bit programmable timer
division ratio selection register (00FF11HD0–D2)
Selects the clock for the 8-bit programmable timer.
It can be selected from 8 types of division ratio
shown in Table 5.5.5.1(a).
This register can also be read.
At initial reset, the PST2 register is set to "0"
(fOSC3/2).
PRPRT2: 8-bit programmable timer
clock control register (00FF11HD3)
Controls the clock supply of the 8-bit program-
mable timer.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
By writing "1" to the PRPRT2 register, the clock
that is selected with the PST2 register is output to
the 8-bit programmable timer.
When "0" is written, the clock is not output.
At initial reset, the PRPRT2 register is set to "0"
(OFF).
PSAD0–PSAD2: A/D converter clock division
ratio selection register (00FF13HD0–D2)
Selects the clock for the A/D converter.
It can be selected from 5 types of division ratio as
shown in Table 5.5.5.1(b).
This register can also be read.
At initial reset, the PSAD register is set to "0"
(fOSC3/1).
PRAD: A/D converter clock control register
(00FF13HD3)
Controls the clock supply of the A/D converter.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
By writing "1" to the PRAD register, the clock that
is selected with the PSAD register is output to the
A/D converter.
When "0" is written, the clock is not output.
At initial reset, the PRAD register is set to "0"
(OFF).
PSF10–PSF12: FOUT1 division ratio selection
register (00FF14HD4–D6)
Selects the frequency for the FOUT1 clock.
It can be selected from 8 types of division ratio
shown in Table 5.5.5.1(b).
This register can also be read.
At initial reset, the PSF1 register is set to "0"
(fOSC1/1).
PRFO1: FOUT1 output control register
(00FF14HD7)
Controls the FOUT1 output.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
When "1" is written to the PRFO1 register, the
FOUT1 (R41) terminal outputs the clock selected
with the PSF1 register. However, the high-imped-
ance control register HZR41 of the output port R41
must be set to "0" and the data register R41D must
be set to "1".
When "0" is written, the clock is not output.
At initial reset, the PRFO1 register is set to "0"
(OFF).
PSF30–PSF32: FOUT3 division ratio selection
register (00FF14HD0–D2)
Selects the frequency for the FOUT3 clock.
It can be selected from 8 types of division ratio
shown in Table 5.5.5.1(b).
This register can also be read.
At initial reset, the PSF3 register is set to "0"
(fOSC3/1).