
58
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
5.4.6 I/O memory of oscillation circuit
Table 5.4.6.1 shows the control bits for the oscillation circuit.
Table 5.4.6.1 Oscillation circuit control bits
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF01
–
Wait state control
CPU operating clock switch
OSC3 oscillation ON/OFF control
VD1 output level setting
–
R/W
–
0
–
OSC1
Off
–
OSC3
On
"0" when being read
–
WT1
WT0
CLKCHG
OSCC
VD1C1
VD1C0
D7
D6
D5
D4
D3
D2
D1
D0
WT1
1
0
WT0
1
0
1
0
Number of states
12(3 cycles)
8(2 cycles)
4(1 cycle)
No wait
VD1C1
1
0
VD1C0
1
0
1
0
VD1 (Typ.)
4.2 V
3.2 V
1.6 V
2.4 V
VD1C0, VD1C1: VD1 output level setting register
(00FF01H D0, D1)
Selects the VD1 level.
Table 5.4.6.2 VD1 settings
VD1C1
1
0
VD1C0
1
0
1
0
Operating
voltage VD1
4.2 V
3.2 V
1.6 V
2.4 V
OSC3 oscillation
ON (0.03–8.8 MHz)
ON (0.03–6.6 MHz)
ON (0.03–1.1 MHz) or OFF
ON (0.03–4.4 MHz)
The VD1 level should be switched according to the
operation of the OSC3 oscillation circuit.
The OSC3 oscillation circuit must be off when
switching the VD1 voltage.
VD1 cannot be switched directly to a level that is
two or three levels different from the current level.
The middle level must be set between switching.
To switch from 1,6 (3.2) V to 3.2 (1.6) V:
1.6 V
→ 2.4 V → 3.2 V
1.6 V
← 2.4 V ← 3.2 V
To switch from 1.6 (4.2) V to 4.2 (1.6) V:
1.6 V
→ 2.4 V → 3.2 V → 4.2 V
1.6 V
← 2.4 V ← 3.2 V ← 4.2 V
To switch from 2.4 (4.2) V to 4.2 (2.4) V:
2.4 V
→ 3.2 V → 4.2 V
2.4 V
← 3.2 V ← 4.2 V
A 5 msec interval is required for each switching
step.
At initial reset, the VD1C register is set to "0" (2.4
V, Typ.).
OSCC: OSC3 oscillation control register
(00FF01HD2)
Turns the OSC3 oscillation circuit on and off.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU and
peripheral circuits (serial interface, programmable
timer, A/D converter, etc.) at high-speed, write "1"
to the OSCC register. At other times, set it to "0" to
reduce current consumption.
At initial reset, the OSCC register is set to "0"
(OSC3 oscillation OFF).
CLKCHG: CPU operating clock switching
register (00FF01HD3)
Selects the operating clock for the CPU.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
When the CPU operating clock is to be OSC3,
write "1" to the CLKCHG register; for OSC1, write
"0".
The OSC3 oscillation circuit takes a maximum 20
msec to stabilize oscillation after turning the OSC3
oscillation circuit on. Therefore, switching the
system clock should be done after the stabilization
time has passed.
At initial reset, the CLKCHG register is set to "0"
(OSC1 clock).