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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 64/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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146
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SIOSEL: Terminal selection register
(00FF40HD7)
Selects the terminals to be used for the serial
interface input/output.
When "1" is written: P14–P17
When "0" is written: P10–P13
Reading: Valid
When "1" is written to the SIOSEL register, the
input/output terminals of the serial interface are
assigned to P14–P17. When "0" is written, they are
assigned to P10–P13. However, the terminals
which are actually used within four the terminals
are decided by the transfer mode setting (SMD
register).
When using IR interface, be sure to set the SIOSEL
register to "1" (P14–P17).
At initial reset, the SIOSEL register is set to "0"
(P10–P13).
SMD0, SMD1: Mode selection register
(00FF40HD1, D2)
Sets the transfer mode as shown in Table 5.14.10.2.
Table 5.14.10.2 Transfer mode settings
SMD1
1
0
SMD0
1
0
1
0
Mode
8-bit asynchronous
7-bit asynchronous
Clock synchronous slave
Clock synchronous master
The SMD register can also be read.
When using IR interface, be sure to set in the
asynchronous mode.
At initial reset, the SMD register is set to "0" (clock
synchronous master mode).
STPB: Stop bit selection register (00FF40HD4)
Selects the stop bit length asynchronous transfer.
When "1" is written: 2 bits
When "0" is written: 1 bit
Reading: Valid
The STPB register is the stop bit selection register
that is valid only for asynchronous transfer. When
"1" is written to the register, the stop bit length is
set in 2 bits. When "0" is written, it is set in 1 bit.
The start bit length is fixed at 1 bit.
The start/stop bit cannot be added for clock
synchronous transfer. Therefore, the setting of the
STPB register is invalid.
At initial reset, the STPB register is set to "0" (1 bit).
EPR: Parity enable register (00FF40HD6)
Selects the parity function.
When "1" is written: With parity
When "0" is written: No parity
Reading: Valid
The EPR register is the parity enable register. By
setting this register, parity check for received data
and addition of a parity bit to transmission data
can be enabled. When "1" is written to the register,
the most significant bit of received data is re-
garded as a parity bit and a parity check is ex-
ecuted and a parity bit is added to transmission
data. When "0" is written, neither a parity check
nor adding a parity bit is done.
This setting is valid only in the asynchronous
mode. It is invalid in the clock synchronous mode.
At initial reset, the EPR register is set to "0" (no
parity).
PMD: Parity mode selection register
(00FF40HD5)
Selects odd parity or even parity.
When "1" is written: Odd parity
When "0" is written: Even parity
Reading: Valid
The PMD register is the parity mode selection
register. When "1" is written to the register, odd
parity is selected. When "0" is written, even parity is
selected. The parity check and addition of a parity bit
are valid only when "1" has been written to the EPR
register. When "0" has been written to the EPR
register, parity setting by the PMD register is invalid.
At initial reset, the PMD register is set to "0" (even
parity).
TXEN: Transmission enable register
(00FF41HD0)
Sets the serial interface to the transmission autho-
rize status.
When "1" is written: Transmission is enabled
When "0" is written: Transmission is disabled
Reading: Valid
The TXEN register is the transmission enable
register. When "1" is written to the register, the
serial interface shifts to a transmission authorize
status. When "0" is written, it shifts to a transmis-
sion disabling status.
Set the TXEN register to "0" when setting the
transfer mode.
At initial reset, the TXEN register is set to "0"
(transmission is disabled).
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