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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 123/250頁 |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
199
CHAPTER 6: SUMMARY OF NOTES
When the segment driver is in self-refresh
status, the OSC3 oscillation can be stopped to
reduce current consumption.
(4) When setting the CPU in SLEEP status, be sure
to turn the LCD panel power off and stop
operation of the LCD controller.
Clock timer
(1) The clock timer actually entqzs into RUN or
STOP status at the falling edge of the 256 Hz
signal after writing to the TMRUN register.
Consequently, when "0" is written to TMRUN,
the timer stops after counting once more (+1).
TMRUN is read as "1" until the timer actually
stops.
Figure 6.2.1 shows the timing chart at the
RUN/STOP control.
TMRUN (WR)
TMDX
57H
58H 59H 5AH 5BH
5CH
TMRUN (RD)
256 Hz
Fig. 6.2.1 Timing chart at RUN/STOP control
(2) The 60-second counter is preset only when data
is written to the TMMD register. The register
does not maintain the preset data and returns
to 0-second when the counter overflows.
To prevent the counter from abnormal opera-
tion, do not preset data without a range of 0 to
59 (BCD).
16-bit programmable timer
(1) The 16-bit programmable timer actually enters
into RUN or STOP status at the falling edge of
the input clock after writing to the PTRUN0(1)
register. Consequently, when "0" is written to
PTRUN0(1), the timer stops after counting once
more (+1). PTRUN0(1) is read as "1" until the
timer actually stops.
Figure 6.2.2 shows the timing chart at the
RUN/STOP control.
PTRUN0/PTRUN1(WR)
PTM0/PTM1
42H
41H 40H 3FH 3EH
3DH
PTRUN0/PTRUN1(RD)
Input clock
Fig. 6.2.2 Timing chart at RUN/STOP control
(2) When the SLP instruction is executed while the
16-bit programmable timer is running
(PTRUN0(1) = "1"), the timer stops counting
during SLEEP status. When SLEEP status is
canceled, the timer starts counting.
However, the operation becomes unstable
immediately after SLEEP status is canceled.
Therefore, when shifting to SLEEP status, stop
the 16-bit programmable timer (PTRUN0(1) =
"0") prior to executing the SLP instruction.
Same as above, the TOUT signal output should
be disabled (PTOUT0(1) = "0") so that an
unstable clock is not output to the clock output
port terminal.
(3) In the 16-bit mode, reading PTM0 does not
latch the timer 1 counter data in PTM1. To
avoid generating a borrow from timer 0 to
timer 1, read the counter data after stopping
the timer by writing "0" to PTRUN0.
8-bit programmable timer
(1) The 8-bit programmable timer actually enters
into RUN or STOP status at the falling edge of
the input clock after writing to the PRUN
register. Consequently, when "0" is written to
PRUN, the timer stops after counting once
more (+1). PRUN is read as "1" until the timer
actually stops.
Figure 6.2.3 shows the timing chart of the
RUN/STOP control.
PRUN (WR)
PTD
42H
41H 40H 3FH 3EH
3DH
PRUN (RD)
Input clock
Fig. 6.2.3 Timing chart at RUN/STOP control
(2) When the SLP instruction is executed while the
8-bit programmable timer is running (PRUN =
"1"), the timer stops counting during SLEEP
status. When SLEEP status is canceled, the
timer starts counting. However, the operation
becomes unstable immediately after SLEEP
status is canceled. Therefore, when shifting to
SLEEP status, stop the 8-bit programmable
timer (PRUN = "0") prior to executing the SLP
instruction.
(3) The prescaler, which supplies the clock to the
8-bit programmable timer, can operate only
when the OSC3 oscillation has been set to ON.
Be aware that the 8-bit programmable timer
does not operate when the OSC3 oscillation
circuit has been turned off.
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