
Chapter 3
Functional Operation
73
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Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
base_addr+Ah right-front sample 1
...
The sample pairs Left-Front/Right-Front, Center-Front/Subwoofer and Left-Rear/Right-Rear can be
swapped by programming DevB:5x4C.
Each FIFO has the following characteristics:
Contains eight 16 bit samples.
Either one 16 bit word (i.e., one sample at a time) or one 32 bit doubleword (i.e., two samples at a
time) can be read or written each clock
using t
he PCI bus.
Transfers to/from the AC-link interface controller are done one sample a frame. The 16 bit
samples are transferred as the 16 most significant bits of each 20 bit slot, with the low order bits
discarded for input data and padded with zeros for output data.
For output buffers (to codec), filling is initiated by completion of passing the one-fourth empty
threshold (i.e., 2 entries are empty, 6 are still full).
For input buffers (from codec), emptying is initiated by completion of passing the one-fourth full
threshold (i.e., 2 entries are full, 6 are still empty).
For a given 2-, 4-, or 6-channel audio configuration two principal transfer modes are supported:
Full Rate Transfer Mode
Half Rate Transfer Mode
In full rate transfer mode all samples for the given audio configuration are transferred in one frame. In
half rate transfer mode the left front, center front, left rear samples are transferred in one frame and
the right front, right rear, subwoofer samples are transferred in the following frame. See Figure 14 and
Figure 15 on page 74 for examples of half rate transfer mode transmissions. When mono audio
sample streams are transferred, software and codec must ensure both left and right samples are
transferring the same data, i.e., for each mono sample two samples are transferred.
The transfer modes are controlled for audio-in samples by the respective valid bits in slot 0 of the
input frame and for audio-out samples by the respective request bits in slot 1 of the input frame. For
audio-out samples a slot 3 request bit set to 0b causes the controller to read all audio samples for a
given audio configuration from the audio-out FIFOs for subsequent transmission as enabled by the
request bits. For audio-in samples a slot 4 valid bit set to 1b causes the controller to write received
audio samples into the audio-in FIFOs. The codec has to send the appropriate valid and request bits in
the correct order as required by the transfer modes. Repeating valid or request bits in subsequent
frames out of order causes loss of data.
For the example in Figure 14 the slot 3, 6, and 7 request bits were set to 0b in Input Frame n-1 with
the slot 3 request bit causing the controller to read audio samples from all audio-out FIFOs.
According to those request bits, slot 3, 6, and 7 samples are transferred in Output Frame n. The slot 4,
8, and 9 request bits active (Low) in Input Frame n cause the controller to send the already read slot 4,
8, and 9 samples in Output Frame n+1. The slot 3 request bit active (Low) in Input Frame n+1 causes
the controller to read new audio samples from all audio-out FIFOs.