參數(shù)資料
型號(hào)： AMD-8151
英文描述： AMD-8151 - Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： AMD的8151 -初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁(yè)數(shù)： 323/378頁(yè)
文件大?。?/td> 3300K
代理商： AMD-8151
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Chapter 4
Registers
323
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
CMD0 is a command-style register. This register is reset by RESET_L. Some bits in this register are
also reset when the RUN bit is cleared.
4
TX_FAST_SPND. Transmit Fast Suspend
. Read-write; write mode R. Setting this bit causes the
transmitter to suspend its activities as quickly as possible without stopping in the middle of a frame
transmission. Setting TX_FAST_SPND does not stop the DMA controller from transferring frame data
from host memory to the transmit FIFO. If a frame is being transmitted at the time that
TX_FAST_SPND is set to 1, the transmission of that frame is completed, but no more frames are
transmitted until TX_FAST_SPND is cleared to 0. After the transmitter has suspended its activity, the
TX_SUSPENDED bit in the Status register and the Suspend Interrupt (SPNDINT) bit in the INT0
register are set, which causes an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in
the Interrupt Enable register is set. This bit is also reset when the RUN bit is cleared.
RX_SPND. Receive Suspend
. Read-write; write mode R. Setting this bit causes the receiver to
suspend its activities without stopping in the middle of a frame reception. After the receiver suspends
its activities, the DMA controller continues copying data from the Receive FIFO into host system
memory until the FIFO is empty. After the Receive FIFO has been emptied, the RX_SUSPENDED bit
in the Status register and the Suspend Interrupt (SPNDINT) bit in the Interrupt register are set. Setting
the SPNDINT bit causes an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in the
Interrupt Enable register is set. This bit is also reset when the RUN bit is cleared.
TX_SPND. Transmit Suspend
. Read-write; write mode R. Setting this bit causes the transmitter to
suspend its activities without stopping in the middle of a frame transmission. The DMA controller
suspends after completing the copying of data from host system memory into the Transmit FIFO for
the current frame (if any). The transmitter continues operation until all frames in the Transmit FIFO
have been transmitted. The TX_SUSPENDED bit in the Status register and the Suspend Interrupt
(SPNDINT) bit in the Interrupt register are then set. Setting the SPNDINT bit causes an interrupt to
occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register is set. This bit
is also reset when the RUN bit is cleared.
INTREN. Interrupt Enable
. Read-write; write mode R. This bit allows INTA to be asserted if any bit in
the Interrupt register is set. If INTREN is cleared to 0, INTA is not asserted, regardless of the state of
the Interrupt register.
RUN. Run bit
. Read-write; write mode R. Setting the RUN bit enables the controller to start
processing descriptors and transmitting and receiving packets. Clearing the RUN bit to 0 abruptly
disables the transmitter, receiver, and descriptor processing logic, possibly while a frame is being
transmitted or received.
The act of changing the RUN bit from 1 to 0 causes the following bits to be reset to 0: TX_SPND,
RX_SPND, TX_FAST_SPND, RX_FAST_SPND, RDMD, all TDMD bits, RINT, all TINT bits, MPINT,
and SPNDINT.
3
2
1
0
Bits
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AMD-8151BLC 制造商:Advanced Micro Devices 功能描述:HyperTransport AGP3.0 Graphics Tunnel
AMD8255A-5 制造商:Advanced Micro Devices 功能描述:8255A-5
AMD8257 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Programmable DMA Controller
AMD850-N14BD 制造商:SMC Corporation of America 功能描述:MICRO MIST SEPARATOR W/ 1-1/4INCH PORTS
AMD8ATCBK 制造商:Wiremold / Legrand 功能描述:FLUSH POKE-THRU ASSY/BK/TC
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