
Chapter 4
Registers
333
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
LAN Ethernet Controller Flow Control
ENC0C8
Default:
Bits
31
0000_0000h
Description
VALBIT3. Value bit for byte 3
. Read-write. The value of this bit is written to any bits in this register
that correspond to any bit of this register set to 1 in the range 30:24.
PAUSE_LEN_CHG. Write mode R. PAUSE Length Change
. Read-write; Before changing the value
of PAUSE_LEN, the host CPU must wait until PAUSE_LEN_CHG = 0 and then write to this register
setting PAUSE_LEN_CHG to 1 and setting PAUSE_LEN to the new value.
29:24 Reserved.
23
VALBIT2. Value bit for byte 2
. Read-write. The value of this bit is written to any bits in this register
that correspond to any bit of this register set to 1 in the range 22:16.
22
FTPE. Write mode N. Force Transmit Pause Enable
. Read-write; When this bit is set, MAC Control
Pause Frames may be transmitted, regardless of the results of autonegotiation.
21
FRPE. Write mode N. Force Receive Pause Enable
. Read-write; When this bit is set, MAC Control
Pause Frames received are recognized and obeyed, regardless of the results of autonegotiation.
20
NAPA. Write mode N. Negotiate Asymmetric Pause Ability
. Read-write; This bit is loaded into the
ASM_DIR advertisement bit of PHY register 4 prior to starting autonegotiation.
19
NPA. Write mode R. Negotiate Pause Ability
. Read-write; This bit is loaded into the PAUSE
advertisement bit of PHY register 4 prior to starting autonegotiation.
18
FIXP. Write mode R. Fixed Length Pause
. Read-write; When this bit is set to 1, all MAC Control
Pause Frames transmitted from the device contain a Request_operand
fi
eld that is copied from the
PAUSE_LEN
fi
eld of this register. When this bit is cleared to 0, a Pause Frame with its
Request_operand
fi
eld set to 0FFFFh is sent when FCCMD is set to 1. A Pause Frame with its
Request_operand
fi
eld cleared to 0000h is sent when FCCMD becomes 0.
17
Reserved.
16
FCCMD. Write mode R. Flow Control Command
. Read-write; This bit can be used by the host to
send Pause Frames or to enable or disable half-duplex back-pressure mode.
In full-duplex mode, if the FIXP bit is 1, FCCMD is a write-only bit. When FCCMD is set to 1, a Pause
Frame is sent with Request_operand copied from the PAUSE_LEN
fi
eld of this register. If the FIXP bit
is 0, FCCMD is a read-write bit. When FCCMD is set to 1, a Pause Frame is sent with its
Request_operand
fi
eld
fi
lled with all 1s. When FCCMD is cleared to 0, a Pause Frame is sent with its
Request_operand
fi
eld
fi
lled with all 0s.
In half-duplex mode, FCCMD is a read-write bit. Setting FCCMD to 1 puts the MAC into back-pressure
mode. Clearing FCCMD to 0 disables back-pressure mode.
15:0
PAUSE_LEN. Write mode R. Pause Length
. Read-write; The contents of this
fi
eld are copied into
the Request_operand
fi
elds of MAC Control Pause Frames that are transmitted while the FIXP pin in
this register has the value 1.
The protocol for changing PAUSE_LEN is:
1) Read FLOW until PAUSE_LEN_CHG is 0.
2) Write FLOW with PAUSE_LEN_CHG = 1 and new value of PAUSE_LEN.
PAUSE_LEN_CHG clears when write is complete, but the driver need not poll for this.
Attribute:
see below.
The upper 16 bits of the FLOW register is a command-style register while the lower 16 bits are a
normal register. This register is reset by RESET_L.
30