
Chapter 6
Pin Designations
361
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
Chapter 6 Pin Designations
Figure 36.
BGA Designations (Top Side View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
NC10
NC12
NC19
NC30
NC21
NC28
DAD
DRS1
DRD
YS
DDAT
AS0
DDAT
AS12
DDAT
AS4
DDAT
AS8
DAD
DRP2
IRQ14
DDR
QP
DDAT
AP13
DDAT
AP3
DDAT
AP9
LDRQ
_L[0]
LAD2
LAD3
IRQ6
VDD_
RTC
LFRA
ME_L
KA20
G
VDD_
REF
A
B
VSS
VSS
VSS
STRA
PH3
STRA
PH0
VSS
DAD
DRS0
VSS
DDAT
AS15
DDAT
AS2
VSS
DDAT
AS6
DCS1
P_L
VSS
DIOW
P_L
DDAT
AP1
VSS
DDAT
AP5
DRST
P_L
VSS
SPKR
LAD0
VSS
IRQ1
VSS
GPIO
26
B
C
VDD_
LDT
VDD_
LDT
VDD_
LDT
VSS
NC29
NC22
DAD
DRS2
IRQ15
DDR
QS
DDAT
AS13
DDAT
AS3
DDAT
AS9
DCS3
P_L
DAD
DRP0
DIOR
P_L
DDAT
AP14
DDAT
AP2
DDAT
AP10
DDAT
AP7
OSC
INTIR
Q8_L
KBRC
_L
SERI
RQ
GPIO
8
VSS
VSS
C
D
LRXC
AD_H
[1]
LRXC
AD_L
[0]
LRXC
AD_H
[0]
VDD_
LDT
STRA
PH1
VDD_
IO
DCS3
S_L
VDD_
IO
DIOR
S_L
DDAT
AS14
VDD_
IO
DDAT
AS10
DDAT
AS7
VDD_
IO
DDAC
KP_L
DDAT
AP15
VDD_
IO
DDAT
AP11
DDAT
AP6
VDD_
IO
LDRQ
_L[1]
LAD1
VDD_
IO
VSS
USB1
_L[0]
USB1
_H[0]
D
E
LRXC
AD_L
[1]
VSS
NC2
STRA
PH2
NC20
NC9
DCS1
S_L
DDAC
KS_L
DIOW
S_L
DDAT
AS1
DDAT
AS11
DDAT
AS5
DRST
S_L
DAD
DRP1
DRD
YP
DDAT
AP0
DDAT
AP12
DDAT
AP4
DDAT
AP8
GPIO
29
PRDY IRQ12
VSS
USB1
_L[1]
USB1
_H[1]
VSS
E
F
LRXC
AD_H
[3]
LRXC
AD_L
[2]
LRXC
AD_H
[2]
VSS
NC7
VSS
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
IO
VDD_
IO
VDD_
IO
VDD_
IO
VSS
TEST
_L
GPIO
31
VSS
USB1
_L[2]
USB1
_H[2]
F
G
LRXC
AD_L
[3]
VSS
LDTC
OMP0
LDTC
OMP1
NC8
VSS
VDD_
CORE
X
CLKR
UN_L
USBO
C_L[0
]
NC31
VSS
VDD_
USB
G
H
NC0
LRXC
LK_L
LRXC
LK_H
VSS
LRXC
AD_H
[4]
VDD_
CORE
VDD_
CORE
X
NC13
USBO
C_L[1
]
NC32
VSS
VDD_
USB
H
J
NC6
VSS
LRXC
AD_H
[5]
LRXC
AD_L
[5]
LRXC
AD_L
[4]
VDD_
CORE
VDD_
CORE
X
VSS_
USBA
USB_
REXT
VSS
USB0
_H[2]
USB0
_L[2]
J
K
LRXC
TL_H
NC15
NC17
VSS
LRXC
AD_H
[6]
VDD_
CORE
VDD_
CORE
X
VDD_
USBA
VSS_
USBA
USB0
_H[1]
USB0
_L[1]
VSS
K
L
LRXC
TL_L
VSS
LRXC
AD_H
[7]
LRXC
AD_L
[7]
LRXC
AD_L
[6]
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
USBA
VSS
VSS
USB0
_H[0]
USB0
_L[0]
L
M
NC11
LTXC
TL_H
LTXC
TL_L
VSS
LTXC
AD_L
[7]
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
IOX
VDD_
IOX
VSS
VSS
VSS
M
N
NC14
VSS
LTXC
AD_L
[6]
LTXC
AD_H
[6]
LTXC
AD_H
[7]
VSS
VSS
VSS
VSS
VSS
VSS
SMB
USD0
RTCX
_OUT
INTR
UDER
_L
RTCX
_IN
S3PL
L_LF
N
P
LTXC
LK_L
NC16
NC18
VSS
LTXC
AD_L
[5]
VSS
VSS
VSS
VSS
VSS
VSS
SMB
USC0
GPIO
14
LDTR
ST_L
S3PL
L_LF
_VSS
PWR
OK
P
R
LTXC
LK_H
VSS
LTXC
AD_L
[4]
LTXC
AD_H
[4]
LTXC
AD_H
[5]
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
IOX
VDD_
IOX
PWR
BTN_
L
VSS
EXTS
MI_L
R
T
LTXC
AD_L
[2]
LTXC
AD_H
[3]
LTXC
AD_L
[3]
VSS
LDTC
OMP2
VSS
VSS
VSS
VSS
VSS
VSS
NC4
DCST
OP_L
RPW
RON
SMB
ALER
T0_L
SLPB
TN_L
T
U
LTXC
AD_H
[2]
VSS
NC5
NC1
LDTC
OMP3
VDD_
CORE
VDD_
CORE
X
SMB
USD1
LID
PWR
ON_L
ACAV
SMB
ALER
T1_L
U
V
LTXC
AD_L
[0]
LTXC
AD_H
[1]
LTXC
AD_L
[1]
VSS
VSS
VDD_
CORE
VDD_
CORE
X
VDD_
IOX
VDD_
IOX
SUSP
END_
L
VSS
SMB
USC1
V
W
LTXC
AD_H
[0]
VSS
VSS
VDD_
LDT
VSS
VDD_
CORE
VDD_
CORE
X
MII_C
OL
MII_C
RS
C32K
HZ
RI_L
BATL
OW_L
W
Y
VDD_
LDT
VDD_
LDT
VDD_
LDT
PIRQ
C_L
PIRQ
A_L
VDD_
CORE
VDD_
CORE
X
MII_T
X_CL
K
MII_R
X_ER
MII_P
HY_R
ST
PME_
L
RESE
T_L
Y
AA
PIRQ
B_L
PIRQ
D_L
AD30
VDD_
IO
AD31
VSS
VSS
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
IO
VDD_
IO
VDD_
IO
VDD_
IO
VDD_
CORE
X
MII_R
X_DV
VDD_
IOX
MII_T
X_EN
VSS
MII_R
X_CL
K
AA
AB
AD29
AD28
AD27
AD16
FRA
ME_L
AD15
AD13
CBE_
L[0]
AD4
AD2
REQ_
L[0]
GNT_
L[2]
REQ_
L[5]
GNT_
L[6]
LDTS
TOP_
L
ACCL
K
STRA
PL2
LDTR
EQ_L
NC24
NC3
STRA
PL0
VDD_
IOX
MII_R
XD1
MII_T
XD1
MII_R
XD0
MII_T
XD0
AB
AC
AD26
VSS
AD25
VDD_
IO
IRDY
_L
CBE_
L[1]
VDD_
IO
AD8
AD3
VDD_
IO
GNT_
L[0]
REQ_
L[3]
VDD_
IO
PNPI
RQ2
FANC
ON_0
VDD_
IO
GPIO
30
STRA
PL3
VDD_
IO
NC23
VDD_
IO
VSS
VDD_
IOX
MII_T
XD3
MII_R
XD2
MII_T
XD2
AC
AD
AD24
CBE_
L[3]
AD20
AD17
TRDY
_L
PERR
_L
AD11
AD12
AD7
AD0
REQ_
L[1]
GNT_
L[3]
GNT_
L[5]
PCLK
PGNT
_L
FANC
ON_1
THER
MTRI
P_L
GPIO
27
GPIO
16
STRA
PL1
NC25
GPIO
4
ACSD
I1
VDD_
IOX
VSS
MII_R
XD3
AD
AE
AD23
VSS
AD19
VSS
DEVS
EL_L
SERR
_L
VSS
AD10
AD6
VSS
GNT_
L[1]
REQ_
L[4]
VSS
PCIST
OP_L
PNPI
RQ0
VSS
CPUS
LEEP
_L
AGPS
TOP_
L
VSS
PREQ
_L
GPIO
17
VSS
NC26
VSS
VDD_
IOX
MII_
MDC
AE
AF
AD22
AD21
AD18
CBE_
L[2]
STOP
_L
PAR
AD14
AD9
AD5
AD1
REQ_
L[2]
GNT_
L[4]
REQ_
L[6]
USBC
LK
PNPI
RQ1
FANR
PM
CPUS
TOP_
L
THER
M_L
ACSD
O
ACSY
NC
NC27
GPIO
28
ACRS
T_L
ACSD
I0
MII_
MDIO
VSS
AF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26