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Chapter 4
Registers
335
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
LAN Ethernet Controller Interrupt 0
ENC038
Default:
Bits
31
0000_0000h
Description
INTR. Interrupt Summary
. Read-only. This bit indicates that one or more of the other interrupt bits in
this register are set and the associated enable bit or bits in INTEN0 are also set. If INTREN in CMD0
is set to 1 and INTR is set, INTA is active. INTR is read-only. INTR is cleared by clearing all of the
active individual interrupt bits that have not been masked out.
INTPN. Interrupt Pin Value
.Read-only. This bit indicates that the INTA_L pin is asserted, that is, both
the INTR bit (INT0[31]) and the INTREN bit (CMD0[1]) are 1.
29:28 Reserved.
27
LCINT. Link Change Interrupt
. Read, write 1b to clear; write mode R. This bit is set when the Port
Manager detects a change in the link status of the external PHY.
26
APINT5. Auto-Poll Interrupt from Register 5
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 5.
25
APINT4. Auto-Poll Interrupt from Register 4
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 4.
24
APINT3. Auto-Poll Interrupt from Register 3
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 3.
23
Reserved.
22
APINT2. Auto-Poll Interrupt from Register 2
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 2.
21
APINT1. Auto-Poll Interrupt from Register 1
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 1.
20
APINT0. Auto-Poll Interrupt from Register 0
. Read, write 1b to clear; write mode R. This bit is set
when the Auto-Poll State Machine has detected a change in the external PHY register whose address
is stored in Auto-Poll Register 0.
19
MIIPDINT. MII PHY Detect Transition Interrupt
. Read, write 1b to clear; write mode R. The MII PHY
Detect Transition Interrupt is set by the controller whenever the MIIPD bit in STAT0 transitions from 0
to 1 or vice versa.
18
Reserved.
17
MCCINT. MII Management Command Complete Interrupt
. Read, write 1b to clear; write mode R.
The MII Management Command Complete Interrupt is set by the controller when a read or write
operation to the MII Data Port (PHY Access Register) is complete.
16
MREINT. MII Management Read Error Interrupt
. Read, write 1b to clear; write mode R. The MII
Read Error interrupt is set by the controller to indicate that the currently read register from the external
PHY is invalid. The contents of the PHY Access Register are incorrect and that the operation should
be performed again. The indication of an incorrect read comes from the PHY. During the read
turnaround time of the MII management frame the external PHY should drive the MDIO pin to a LOW
state. If this does not happen, it indicates that the PHY and the controller have lost synchronization.
15
Reserved.
14
SPNDINT. Suspend Interrupt
. Read, write 1b to clear; write mode R. his bit is set when a receiver or
transmitter suspend operation has
fi
nished.
Attribute:
see below.
30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMD64 | AMD64 Architecture Programmer＇s Manual Volume 1: Application Programming |
| AMDATHLON | AMD Athlon - AMD Athlon Processor Model 4 Revision Guide |
| AMDATHLON64 | AMD Athlon 64 - Report of Management on Processor Performance Benchmarks AMD Athlon 64 Processor 3200+ |
| AMDATHLONMP | AMD Athlon MP - AMD Athlon MP Processor Model 6 Data Sheet |
| AMDATHLONXP | AMD Athlon XP - AMD Athlon XP Processor Model 8 Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-8151BLC | 制造商:Advanced Micro Devices 功能描述:HyperTransport AGP3.0 Graphics Tunnel |
| AMD8255A-5 | 制造商:Advanced Micro Devices 功能描述:8255A-5 |
| AMD8257 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Programmable DMA Controller |
| AMD850-N14BD | 制造商:SMC Corporation of America 功能描述:MICRO MIST SEPARATOR W/ 1-1/4INCH PORTS |
| AMD8ATCBK | 制造商:Wiremold / Legrand 功能描述:FLUSH POKE-THRU ASSY/BK/TC |
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