參數(shù)資料
型號(hào)： AMD-8151
英文描述： AMD-8151 - Preliminary AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Data Sheet
中文描述： AMD的8151 -初步的AMD - 8151 HyperTransport的AGP3.0圖形隧道數(shù)據(jù)表
文件頁(yè)數(shù)： 123/378頁(yè)
文件大?。?/td> 3300K
代理商： AMD-8151
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Chapter 3
Functional Operation
123
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
Received MAC Control PAUSE frames are handled completely by the hardware. They are not passed
on to the host computer. However, MAC Control frames with opcodes not equal to 0001h are treated
as normal frames, except that their reception causes the Unsupported Opcodes counter to be
incremented.
Since the host computer does not receive MAC Control PAUSE frames, 32-bit MIB counters have
been added to record the following:
MAC Control Frames received
Unsupported Opcodes received
PAUSE frames received
3.10.15
Delayed Interrupts
To reduce the host CPU interrupt service overhead the network controller can be programmed to
postpone the interrupt to the host CPU until either a programmable number of receive or transmit
interrupt events have occurred or a programmable amount of time has elapsed since the first interrupt
event occurred. The use of the Delayed Interrupt Registers allows the interrupt service routine to
process several events at one time without having to return control back to the operating system
between events.
A receive interrupt event occurs when receive interrupts are enabled, and the network controller has
completed the reception of a frame and has updated the frame's descriptors. A receive interrupt event
causes the Receive Interrupt (RINT0) bit in the INT0 Register to be set if it is not already set.
Similarly a transmit interrupt event occurs when transmit interrupts are enabled, and the network
controller has copied a transmit frame's data to the transmit FIFO and has updated the frame's
descriptors. A transmit interrupt event causes the appropriate Transmit Interrupt (TINTx) bit in the
INT0 Register to be set if it is not already set. Note that frame receptions or transmissions affect the
interrupt event counter only when the corresponding receive or transmit interrupts are enabled.
The network controller contains two Delayed Interrupt Registers that can be programmed to delay
two groups of interrupts. Corresponding to each Delayed Interrupt Register is an Interrupt Group
Register that selects which interrupt events are included in each group.
Each Interrupt Group Register has five Include bits, DLY_INT_x_T[3:0] and DLY_INT_x_R0, that
correspond to transmit interrupts (TINT[3:0]) for each of 4 priority levels and the receive interrupt.
The x in DLY_INT_x stands for A for group A interrupts and for B in group B interrupts. For each
Include bit that is set in a particular Interrupt Group Register, the corresponding interrupt event is
included in the interrupt group. Any interrupt event that is included in an interrupt group is delayed
until the conditions programmed into the corresponding Delayed Interrupt Register are met.
Each Delayed Interrupt Register contains a 5-bit Event Count field and a 11-bit Maximum Delay
Time field.
Each time the host CPU clears a RINT or TINT bit that corresponds to an interrupt event that is
included in an interrupt group, the contents of the Event Count field of the corresponding Delayed
Interrupt Register are loaded into an internal interrupt event counter, the contents of the Maximum
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AMD-8151BLC 制造商:Advanced Micro Devices 功能描述:HyperTransport AGP3.0 Graphics Tunnel
AMD8255A-5 制造商:Advanced Micro Devices 功能描述:8255A-5
AMD8257 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Programmable DMA Controller
AMD850-N14BD 制造商:SMC Corporation of America 功能描述:MICRO MIST SEPARATOR W/ 1-1/4INCH PORTS
AMD8ATCBK 制造商:Wiremold / Legrand 功能描述:FLUSH POKE-THRU ASSY/BK/TC
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