
Chapter 3
Functional Operation
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24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
3.7.2
Serial IRQ Protocol
The IC supports the serial IRQ protocol. This logic controls the SERIRQ pin and outputs IRQs to the
PIC and IOAPIC blocks. This logic runs off of PCLK. It is specified by DevB:3x4A. The serial IRQ
logic does not provide support for generating IRQ0, IRQ2, IRQ8, or IRQ13. In order to use IRQ[15,
14, 12, 6, or 1], the corresponding external IRQ pin must be pulled High. The PCI IRQs from the
serial IRQ logic are routed to the interrupts specified by DevB:3x56.
3.7.3
SMBus 1.0
The IC includes a system management bus 1.0, or SMBus 1.0, interface. SMBus is a two-wire serial
interface typically used to communicate with system devices such as temperature sensors, clock
chips, and batteries. The control registers for this bus are PME0 through PMEF.
The SMBus interface includes a host controller and a host-as-slave controller.
Host controller.
The host controller is used to generate cycles over the SMBus as a master. Software
accomplishes this by setting up PME2[CYCTYPE] to specify the type of SMBus cycle desired and
then (or concurrently) writing a 1 to PME2[HOSTST]. This triggers an SMBus cycle with the
address, command, and data fields as specified by the registers called out in PME2[CYCTYPE].
Writes to the host controller registers PME2[3:0], PME4, PME8, and PME9 are illegal while the host
is busy with a cycle. If a write occurs to PME2 while PME0[HST_BSY] is active, then the four LSBs
are ignored. Writes to PME4, PME8, and PME9 while PME0[HST_BSY] is active are ignored (the
transaction is completed, but no data is transferred to the SMBus controller).
If an SMBus-defined time out occurs while the host is master of the SMBus, then the host logic
attempts to generate a SMBus stop event to clear the cycle and PME0[TO_STS] is set.
The host controller is only available in the FON state.
Host-as-slave controller.
The host-as-slave controller responds to word-write accesses to either the
host address specified by PMEE or the snoop address specified by PMEF. In either case, if the address
matches, then the subsequent data is placed in PMEC and PMEA. In the case of snoop accesses, the
command information is stored in PMEC[7:0] and the data is stored in PMEA[15:0]. In the case of
addresses that match the PMEE host-as-slave address register, then the address is stored in
PMEC[7:1]—if the transaction includes a 7-bit address—or PMEC[15:1]—if the transaction includes
a 10-bit address. After the address match is detected, the logic waits for the subsequent stop command
before setting the appropriate status bits in PME0[HSLV_STS, SNP_STS]; however, if a time out
occurs during the cycle, after the address match is detected, then the appropriate bits in
PME0[HSLV_STS, SNP_STS] are set.
If one of the slave status bits, PME0[HSLV_STS, SNP_STS], is set and another access to the host
slave controller is initiated, then it is not acknowledged by the first SMBus acknowledge cycle until
the status bit is cleared.
The host-as-slave controller operates in all system power states except MOFF; it can be used to
generate interrupts and resume events.