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MB90560 series
APPENDIX B INSTRUCTIONS
517
Table B.8-11 Shift instructions (byte, word, long-word): 18 instructions
*1 6 when R0 is zero, 5 + (R0) otherwise
*2 6 when R0 is zero, 5 + (R0) otherwise
<Caution>
See Table B.5-1, "Number of execution cycles for each type of addressing," and Table B.5-2,
"Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
Mnemonic
RORC A
ROLC
#
2
2
~
RG
0
0
B
0
0
Operation
LH AH
-
-
I
-
-
S
-
-
T
-
-
N
Z
V
-
-
C
RMW
-
-
A
RORC ear
RORC eam
ROLC
ROLC
ear
eam
ASR
LSR
LSL
A,RO
A,RO
A,RO
2
2+
2
2+
2
2
2
2
2
3
5+(a)
3
5+(a)
*1
*1
*1
2
0
2
0
1
1
1
0
2×(b)
0
2×(b)
0
0
0
byte (A)
←
Right rotate with carry
byte (A)
←
Left rotate with carry
byte (ear)
←
Right rotate with carry
byte (eam)
←
Right rotate with carry
byte (ear)
←
Left rotate with carry
byte (eam)
←
Left rotate with carry
byte (A)
←
Arithmetic right barrel shift (A,R0)
byte (A)
←
Logical right barrel shift (A,R0)
byte (A)
←
Logical left barrel shift (A,R0)
word (A)
←
Arithmetic right shift (A,1 bit)
word (A)
←
Logical right shift (A,1 bit)
word (A)
←
Logical left shift (A,1 bit)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
-
-
-
-
-
-
-
-
-
-
-
-
ASRW
LSRW
SHRW A
LSLW
SHLW A
A
A /
A /
ASRW
LSRW
LSLW
A,R0
A,R0
A,R0
1
1
1
2
2
2
2
2
2
*1
*1
*1
0
0
0
1
1
1
0
0
0
0
0
0
word (A)
←
Arithmetic right barrel shift (A,R0)
word (A)
←
Logical right barrel shift (A,R0)
word (A)
←
Logical left barrel shift (A,R0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ASRL
LSRL
LSLL
A,R0
A,R0
A,R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A)
←
Arithmetic right barrel shift (A,R0)
long (A)
←
Logical right barrel shift (A,R0)
long (A)
←
Logical left barrel shift (A,R0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-