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型號(hào)：	MB90F562
廠商：	Fujitsu Limited
英文描述：	Octal Bus Transceivers And Registers With 3-State Outputs 24-CDIP -55 to 125
中文描述：	16位微控制器
文件頁(yè)數(shù)：	133/581頁(yè)
文件大?。?/td>	3144K
代理商：	MB90F562

MB90560 series

CHAPTER 5 LOW POWER CONSUMPTION MODE

Figure 5.5-3 Release of timebase timer mode (by an external reset)

Return to normal mode by an interrupt

If an interrupt request of level 7 or higher is issued from a peripheral circuit in timebase timer

mode (when IL2, IL1, and IL0 of the interrupt control register (ICR) are set to a value other than

”), the low power consumption control circuit releases timebase timer mode. After the

release, the CPU handles the interrupt in a normal manner. The CPU executes processing

according to the settings of the I flag of the condition code register (CCR), interrupt level mask

interrupt processing. If the interrupt is not accepted, the CPU resumes execution with the

instruction that follows the instruction in which switching to timebase timer mode was specified.

When interrupt processing is executed normally, the CPU first executes the instruction that

follows the instruction in which switching to timebase timer mode was specified. The CPU

then proceeds to interrupt processing.

PLL clock oscillation stabilization wait interval on release of timebase timer mode

The period from the falling edge to the rising edge of the timebase timer output (2

x oscillation

clock cycle) is allowed for the detection of the end of the PLL clock oscillation wait interval.

When timebase timer mode is released by an external reset or an interrupt, the timebase timer

itself is not cleared. Consequently, a delay of a maximum of one cycle (2 x 2

x oscillation clock

cycle) occurs until the falling edge of the timer output has actually been detected after timebase

timer mode is released.

Therefore, a certain amount of time (2

x oscillation clock cycle to 3 x 2

x oscillation clock

cycle) is required before PLL clock operation begins after the release of timebase timer mode.

The CPU and peripheral functions operate using the main clock until the switch to the PLL clock.

CPU operation

Oscillation stabilization wait

Reset sequence

Reset released.

Timebase timer mode released

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