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CHAPTER 6 INTERRUPTS
MB90560 series
6.3
6.3.2 Interrupt control register functions
Interrupt Control Registers and Peripheral Functions
The interrupt control registers (ICR00 to ICR15) consist of the following four functional
bits:
Interrupt level setting bits (IL2 to IL0)
Extended intelligent I/O service (EI
2
OS) enable bit (ISE)
Extended intelligent I/O service (EI
2
OS) channel selection bits (ICS3 to ICS0)
Extended intelligent I/O service (EI
2
OS) status (S1 to S0)
I
Configuration of interrupt control registers (ICR)
Figure 6.3-3 shows the configuration of the interrupt control register (ICR) bits.
Figure 6.3-3 Configuration of interrupt control registers (ICR)
Reference
The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI
2
OS) has
been activated. To activate EI
2
OS, set the ISE bit to 1. To not activate EI
2
OS, set the ISE
bit to 0. When EI
2
OS is not activated, setting ICS3 to ICS0 is optional.
ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading.
I
Interrupt control register functions
G
Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt level of the corresponding peripheral function. These bits are
initialized to level 7 (no interrupts) by a reset.
Table 6.3-2 shows the correspondence between the interrupt level setting bits and interrupt
levels.
Writing to interrupt control register (ICR)
Address
0000B0
H
to
0000BF
H
Reading of interrupt control register (ICR)
Address
0000B0
H
to
0000BF
H
Initial value
Initial value
R:
W:
- :
Read-only
Write-only
Not used