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4
CHAPTER 1 OVERVIEW
MB90560 series
1.2
Product Lineup
Table 1.2-1 shows the product lineup of the MB90560 series. The specifications
excluding the ROM and RAM capacities are common for the series.
I
Product Lineup
Table 1.2-1 Product lineup of the MB90560 series
Device
MB90V560
MB90F562
MB90561
MB90562
Type
Evaluation device
Flash Type ROM
Mass-production product (mask ROM)
ROM size
—
64K Byte
32K Byte
RAM size
4K Byte
2K Byte
1K Byte
CPU function
Number of basic instructions
Minimum instruction execution time: 62.5 ns/4 MHz (when PLL clock is multiplied
by 4)
Number of addressing modes
: 23
Program patch function
: 2-address pointer
Maximum memory address space : 16M bytes
: 351
Port
I/O ports (CMS): 50
UART
With a full duplex double buffer. Capable of synchronous or asynchronous clock
transfer. Usable also for serial I/O. Dedicated built-in baud rate generator. Two
channels built-in
16-bit reload
timer
16-bit reload timer operation (toggle output or one-shot selectable) Choice of the
event count function. Two channels built-in.
Advanced timer
16-bit free running timer x 1 channel, 16-bit output compare x 6 channels, 16-bit
input capture x 4 channels
8-/16-bit PPG timer (8-bit mode x 6 channels, 16-bit mode x 3 channels)
Waveform generation circuit: 8-bit timer x 3 channels
Three-phase waveform output, dead time output
10-bit A/D con-
verter
10-bit resolution x 8 channels (input multiplex)
Conversion time:6.13
μ
or less (operation at internal 16 MHz clock)
External inter-
rupt
Independent 8 channels
Interrupt cause: L-to-H edge, H-to-L edge, L-level, or H-level selectable
Low-power con-
sumption mode
Sleep mode, stop mode, and CPU intermittent mode
Process
CMOS
Package
PGA256
QFP-64 (0.65 or 1.00 mm pitch), SHDIP-64
Operating volt-
age
5V±10% @16MHz