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CHAPTER 5 LOW POWER CONSUMPTION MODE
MB90560 series
5.4
CPU Intermittent Operation Mode
CPU intermittent operation mode is used for intermittent operation of the CPU while
peripheral functions continue to operate at high speed. Its purpose is to reduce power
consumption.
I
CPU intermittent operation mode
CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period.
The halt occurs after the execution of every instruction that accesses a register, internal memory
(ROM and RAM), I/O, peripheral functions. and the external bus. Internal bus cycle activation is
therefore delayed. While a steady rate of peripheral clock pulses are supplied to the peripheral
functions, the rate of CPU execution is reduced, enabling processing with low power
consumption.
The CG1 and CG0 bits of the low power mode control register (LPMCR) are used to select
the number of clock pulses per halt cycle of the clock supplied to the CPU.
Instruction execution time in CPU intermittent mode can be calculated. A correction value
should be obtained by multiplying the number of times instructions that access a register,
internal memory and internal peripheral functions are executed by the number of clock pulses
per halt cycle. Add this correction value to the normal execution time.
Figure 5.4-1 shows the operating clock pulses during CPU intermittent operation mode.
Figure 5.4-1 Clock pulses during CPU intermittent operation
Peripheral clock
CPU clock
Halt cycle
One instruction
execution cycle
Internal bus activation