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CHAPTER 2 CPU
MB90560 series
2.1
CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for use in applications, such as
consumer and mobile equipment, which require high-speed real-time processing. The
instruction set of the F2MC-16LX was designed for controllers so that it can perform
various types of control at high speeds and efficiencies.
The F2MC-16LX CPU core process not only 16-bit data but also 32-bit data using a built-
in 32-bit accumulator. Memory space, which can be extended up to 16M bytes, can be
accessed in either linear or bank access mode. The instruction set inherits the AT
architecture of F2MC-8L, and has additional instructions supporting high-level
languages. In addition, it has an extended addressing mode, enhanced multiply/divide
instructions, and reinforced bit manipulation instructions.
I
CPU
G
Minimum instruction execution time: 62.5 ns (source oscillation at 4 MHz and PLL clock
multiplication by 4)
G
Maximum memory address space: 16M bytes. Access in linear or bank mode
G
Instruction set optimum for controller applications
Many data types (bit, byte, word, and long word)
As many as 23 addressing modes
Enhanced high-precision arithmetic operation by a 32-bit accumulator
Enhanced signed multiply/divide instructions and RETI instruction function
G
Enhanced interrupt function
Eight programmable priority levels
G
Automatic transfer function independent of CPU
Extended intelligent I/O service using up to 16 channels
G
Instruction set supporting high-level language (C language) and multitasking
System stack pointer, instruction set symmetry, and barrel shift instructions
G
Increased execution speed: 4-byte instruction queue
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The MB90560 series runs only in single-chip mode so only internal ROM and RAM and
internal peripheral address space can be accessed.