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型號(hào)：	MB90F562
廠商：	Fujitsu Limited
英文描述：	Octal Bus Transceivers And Registers With 3-State Outputs 24-CDIP -55 to 125
中文描述：	16位微控制器
文件頁(yè)數(shù)：	327/581頁(yè)
文件大小：	3144K
代理商：	MB90F562

MB90560 series

CHAPTER 12 MULTI-FUNCTION TIMER

Table 12.3.2.2-2 Compare Control Register (Lower, OSC0/2/4)

Compare match

interrupt flag bit

This bit is an interrupt flag for when compare register 1/3/5 is

matched with the value of 16-bit free-run timer.

'1' is written to this bit when the compare register value matches

the 16-bit free-run timer value.

While the interrupt request bits (IOE1) is enabled, an output

compare interrupt occurs when the IOP1 bit is set.

Writing “0” will clear this bit.

Writing “1” has no effect.

In Read-Modify-Write operation, “1” is always read.

Compare match

interrupt flag bit

This bit is an interrupt flag for when compare register 0/2/4 is

matched with the value of 16-bit free-run timer.

'1' is written to this bit when the compare register value matches

the 16-bit free-run timer value.

While the interrupt request bits (IOE0) is enabled, an output

compare interrupt occurs when the IOP0 bit is set.

Writing “0” will clear this bit.

Writing “1” has no effect.

In Read-Modify-Write operation, “1” is always read.

Compare match

interrupt enable

This bit is used to enable output compare interrupt for compare

While the '1' is written to this bit, an output compare interrupt

occurs when an interrupt flag (IOP1) is set.

Compare match

interrupt enable

This bit is used to enable output compare interrupt for compare

While the '1' is written to this bit, an output compare interrupt

occurs when an interrupt flag (IOP0) is set.

The read value is indeterminate.

Writing to this bit has no effect on the operation.

This bit is used to enable the compare operation between 16-bit

free-run timer and compare register 1/3/5

Ensure that a value is written into the compare register and

timer data register before the compare operation is enabled.

Since output compare is synchronized with the 16-bit

free-run timer clock, stopping the 16-bit free-run timer

stops compare operation.

This bit is used to enable the compare operation between 16-bit

free-run timer and compare register 0/2/4

Ensure that a value is written into the compare register and

timer data register before the compare operation is enabled.

Since output compare is synchronized with the 16-bit

free-run timer clock, stopping the 16-bit free-run timer

stops compare operation.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MB90F562BPMC-GE1	制造商:FUJITSU 功能描述:
MB90F562PMCR-GE1	制造商:FUJITSU 功能描述:
MB90F568PMCR-GE1	制造商:FUJITSU 功能描述:
MB90F583BPFR-GE1	制造商:FUJITSU 功能描述:
MB90F583BPMC-GE1	制造商:FUJITSU 功能描述:

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