![](http://datasheet.mmic.net.cn/330000/MB90F562_datasheet_16437954/MB90F562_263.png)
MB90560 series
CHAPTER 10 WATCHDOG TIMER
239
10.2 Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
Count clock selector
Watchdog counter (2-bit counter)
Watchdog reset generator
Counter clear control circuit
Watchdog timer control register (WDTC)
I
Block diagram of the watchdog timer
Figure 10.2-1 shows the block diagram of the watchdog timer.
Figure 10.2-1 Block diagram of the watchdog timer
G
Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of timebase
timer outputs. This determines the watchdog reset generation time.
G
Watchdog counter (2-bit counter)
This 2-bit up counter uses the timebase timer output as the count clock.
G
Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
G
Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
G
Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
Watchdog timer control register (WDTC)
Watchdog timer
Start of sleep mode
Start of hold status mode
Start of stop mode
Counter
clear control
circuit
Count
clock
selector
Activation
with CLR
2-bit
counter
Over-
flow
Watchdog
reset generator
To the internal
reset generator
Clear
(Timebase timer counter)
One-half of HCLK
HCLK: Oscillation clock