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CHAPTER 16 8/10-BIT A/D CONVERTER
MB90560 series
16.6
16.6.2 A/D conversion data protection function
Operation of the 8/10-Bit A/D Converter
When A/D conversion is performed in the interrupt enabled state, the conversion data
protection function operates.
I
A/D conversion data protection function
The A/D converter has just one data register that holds conversion data. When a single A/D
conversion is completed, the data in the data register is rewritten.
If the conversion data were not transferred to memory before the next conversion data was
stored, part of the conversion data would be lost. The data protection function operates in the
interrupt enabled state (INTE = 1), as described below, to prevent loss of data.
G
Data protection function when EI2OS is not used
When conversion data is stored in the A/D data register (ADCR), the INT bit of the A/D control
status register 1 (ADCS1) is set to “1”.
While the INT bit is “1”, A/D conversion is halted.
Halt status is released when the INT bit is cleared after data in the A/D data register (ADCR) has
been transferred to memory by the interrupt routine.
G
Data protection function when EI2OS is used
In continuous conversion using EI2OS, the PAUS bit of the A/D control status register1 (ADCS1)
is kept at “1” when a conversion ends. This status continues until EI2OS finishes transferring the
conversion data from the data register to memory. In the meantime, the A/D conversion is
halted, and the next conversion data is not stored. When the data transfer to memory is
completed, the PAUS bit is cleared to “0”, conversion and conversion resumes.
Figure 16.6-5 shows the operation flow of the data protection function when EI2OS is used.