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CHAPTER 5 LOW POWER CONSUMPTION MODE
MB90560 series
5.2
Block Diagram of the Low Power Consumption Control
Circuit
The low power consumption control circuit consists of the following seven blocks:
CPU intermittent operation selector
Standby clock control circuit
CPU clock control circuit
Peripheral clock control circuit
Pin high-impedance control circuit
Internal reset generation circuit
Low power mode control register (LPMCR)
I
Block diagram of the low power consumption control circuit
Figure 5.2-1 shows the block diagram of the low power consumption control circuit.
Figure 5.2-1 Block diagram of the low power consumption control circuit
X0
2
X1
RST
RST
STP
RST
SLP
CG1
CG0
RESV
SPL
RESV
RESV
WS0
MCM
MCS
CS1
CS0
WS1
RESV
2
2
Low power mode control register (LPMCR)
Pin
Pin
Pin
Divide-
by-2
Divide-
by-2048
Divide-
by-4
Divide-
by-4
Divide-
by-8
PLL multipiller
circuit
System clock
generation circuit
Timebase timer
Stop signal
Release reset
Cancel interrupt
CPU clock
Pin Hi-z control
Clock selector
Clock selection register (CKSCR)
Stop and sleep signals
Machine clock
Main clock
Oscillation stabilization
wait interval selector
Oscillation stabiliz-
-ation wait is passed
CPU clock
control circuit
Pin high
impedance
control circuit
Internal reset
generation
circuit
Internal reset
Peripheral clock
control circuit
CPU intermittent
operation selecter
Select intermittent cycles
Standby control
circuit
Peripheral clock
Clock generator