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CHAPTER 13 UART
MB90560 series
13.4
13.4.3 Serial Status Register (SSR0/1)
UART Registers
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
I
Serial Status Register (SSR0/1)
Figure 13.4-4 Status register (SSR0/1)
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8 bit7
bit0
(SIDR/SODR)
TIE
RIE
BDS
TDRE
RDRF
FRE
ORE
PE
TIE
0
1
R
R
R
R
R
R/W
R/W
ch0:000023
H
ch1:000027
H
0 0 0 0 1 0 0 0
B
RIE
0
1
BDS
0
1
TDRE
0
1
RDRF
0
1
0
1
FRE
ORE
0
1
R/W
R
R/W
PE
0
1
: Read/Write
: Read only
: Initial value
Transmission interrupt request enable bit
Disables transmission interrupt request.
Enables transmission interrupt request.
Reception enable bit
Disables reception interrupt request.
Enables reception interrupt request.
Transfer direction selection bit
LSB first (transfer from the least significant bit)
MSB first (transfer from the most significant bit)
Transmission data empty flag bit
Transmission data exists.
(Writing transmission data is not allowed.)
Transmission data does not exist.
(Writing transmission data is allowed.)
Receive data full flag bit
No receive data exists.
Receive data exists.
Framing error flag bit
No framing error occurred.
A framing error occurred.
Overrun error flag bit
No overrun error occurred.
An overrun error occurred.
Parity error flag bit
No parity error occurred.
A parity error occurred.
Address
Initial value