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MB90560 series
APPENDIX B INSTRUCTIONS
499
G
Register indirect addressing with base index (@RW0+RW7, @RW1+RW7)
This type of addressing accesses memory at an address determined by adding the contents of
general-purpose register RW7 to RW0 or RW1. Address bits 16 to 23 are specified by the DTB
register. Figure B.4-6 shows an example of register indirect addressing with a base index
(@RW0+RW7, @RW1+RW7).
Figure B.4-6 Example of register indirect addressing with base index (@RW0+RW7, @RW1+RW7)
G
Program counter relative branch addressing (rel)
A branch destination address is represented as the program counter (PC) value plus an 8-bit
displacement. Because the bank register is not incremented or decremented and overflow is
ignored if the result is over 16 bits, the result is an address within the 64-kilobyte bank.
This addressing method is used for unconditional and conditional branch instructions. Address
bits 16 to 23 are specified by the PCB register. Figure B.4-7 shows an example of program
counter relative branch addressing (rel).
Figure B.4-7 Example of program counter relative branch addressing (rel)
After execution
Before execution
Memory space
MOVW A, @RW1+RW7 (Instruction that reads data by register indirect
addressing with base index and stores it in A)
Next instruction
After execution
Before execution
Memory space
BRA 3B20H (Unconditional relative branch instruction)