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CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT
MB90560 series
14.4
14.4.2 DTP/interrupt enable register (ENIR)
DTP/External Interrupt Circuit Registers
The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt
requests to the CPU.
I
DTP/interrupt enable register (ENIR)
Figure 14.4-3 DTP/interrupt enable register (ENIR)
Table 14.4-2 Function description of each bit of the DTP/interrupt enable register (ENIR)
Bit name
Function
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7 to EN0:
External interrupt
request enable bits
Each of these bits enables and disables interrupt requests to
the CPU. If these bits and corresponding bits ER7 to ER0 of
the DTP/interrupt cause register (EIRR) are “1”, an interrupt
request is output to the CPU.
[Reference]
To use a DTP/external interrupt pin, write “0” to the corre-
sponding bit of the port direction register to set the pin as
an input port.
The states of the DTP/external interrupt pins can be read
directly using the port data register regardless of the states
of external interrupt request enable bits.
Bits ER7 to ER0 of the DTP/interrupt cause register (EIRR)
are set to “1” if an interrupt cause is detected regardless of
the values of external interrupt request enable bits.
Address
R/W R/W
R/W R/W
Initial value
(EIRR)
0 0 0 0 3 0
H
EN7 EN6 EN5 EN4 EN3
EN2
EN1 EN0
00000000
B
External interrupt request enable bits
0
1
An external interrupt request is disabled.
An external interrupt request is enabled.
EN7
EN0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15
bit8
R/W R/W
R/W R/W
R/W : Read/write enabled
:
Initial value