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CHAPTER 9 TIMEBASE TIMER
MB90560 series
9.4
Timebase Timer Interrupts
The timebase timer can generate an interrupt request when the bit specifying the
timebase timer counter overflows. (Interval timer function)
I
Timebase timer interrupts
The interrupt request flag bit (TBTC:TBOF) is set to “1” when the timebase timer counter counts
up with the internal count clock and when the bit for the selected interval timer bit overflows. If
the interrupt request enable bit has been enabled (TBTC:TBIE = 1), an interrupt request (#36) is
generated in the CPU. Writing “0” to the TBOF bit in the interrupt handling routine clears the
interrupt request. When the specified bit overflows, the TBOF bit is set regardless of the TBIE bit
value.
<Check>
Clear the interrupt request flag bit (TBTC:TBOF) while a timebase timer interrupt is disabled
by setting the TBIE bit or the processor status (PS) ILM bit.
Reference
When the TBOF bit is “1”, if the TBIE bit status is switched from disable to enable (0
→
1),
an interrupt request occurs immediately.
The timebase timer cannot use the extended intelligent I/O service (EI
2
OS).
I
Timebase timer interrupts and EI
2
OS
Table 9.4-1 lists the timebase timer interrupt and EI2OS.
Table 9.4-1 Timebase interrupts and EI
2
OS
x: Not available
<Check>
ICR12 is common to the timebase timer interrupt and input capture ch 2/3 wake-up interrupt.
Interrupts can be used for two applications, but the interrupt level is the same.
Interrupt
number
Interrupt level setting
register
Vector table address
EI
2
OS
Register name
Address
Lower
Upper
Bank
#36 (24
H
)
ICR12
0000BC
H
FFFF6C
H
FFFF6D
H
FFFF6E
H
x