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CHAPTER 12 MULTI-FUNCTION TIMER
MB90560 series
I
Making non-overlap signals by using PPG
When selecting non-overlap signal for a active level “0” (positive polarity) in DTCR:bit 15 (DMOD), a
delay corresponding to the non-overlap time set in the TMRR register (8-bit reload register) is applied.
The delay is applied at a rising edge of PPG timer pulse signal or its inverted signal. If PPG timer pulse
width is smaller than the set non-overlap time, the 8-bit timer will start counting from “00
H
” at the next
edge of PPG pulse.
Figure 12.4.5.1-3 Positive Polarity Non-overlap Signal Generation by PPG timer
Setting up registers:
TCDT
TCCS
OCCP0~5
TMRR0~2
SIGR
Note:
: 0000
H
: ------XXXX0X0XXX
B
: XXXX
H
(Compare value)
: XXXXXXXXX
B
(non-overlap timing setting)
: XXXXXX00
B
(DTTI input and 8-bit timer count clock setting)
“X” must be set according to the operation.
CPCLR
OSC0~5
DTCR0~2
: XXXX
H
(Cycle setting)
: ---1XXXXXXXX--11
B
: 01000111
B
Count
Value
PPG1
U
X
one machine cycle
one machine cycle
TMRR set value
Pin name
Output signal
U
Signal with delay is applied at PPG1 rising edge
V
Signal with delay is applied at PPG3 rising edge
W
Signal with delay is applied at PPG5 rising edge
X
Signal with delay is applied at PPG1 falling edge
Y
Signal with delay is applied at PPG3 falling edge
Z
Signal with delay is applied at PPG5 falling edge