TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
76
Agere Systems Inc.
8 TMUX Registers
(continued)
Table of Contents
(continued)
Tables
Page
Table 121. TMUX_SF_CTL[1
—
6], B1/B2 Signal Fail Set/Clear Control Registers (R/W) ................................... 117
Table 122. TMUX_B3SD_CTL[1
—
6], B3 Signal Degrade Set/Clear Control Registers (R/W) ........................... 117
Table 123. TMUX_B3SF_CTL[1
—
6], B3 Signal Fail Set/Clear Control Registers (R/W) .................................... 118
Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO) .............................................................................. 118
Table 125. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO) ..................... 119
Table 126. TMUX_B3ECNT[1
—
3], Receive B3 Error Counts (RO) .................................................................... 119
Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO) ................... 120
Table 128. TMUX_G1ECNT[1
—
3], Receive G1 Error Counts (RO) ................................................................... 120
Table 129. TMUX_RPTR_INCCNT[1
—
3], Receive Pointer Increment Count (RO) ............................................ 121
Table 130. TMUX_RPTR_DECCNT[1
—
3], Receive Pointer Decrement Count (RO) ......................................... 121
Table 131. TMUX_RJ0EXPECTED[1
—
8], Expected J0 Byte Sequence (R/W) ................................................. 121
Table 132. TMUX_RJ0CAPTURED[1
—
8], Captured J0 Receive Value (RO) .................................................... 121
Table 133. TMUX_TJ0VALUE[1
—
8], J0 Byte Transmit Insert (R/W) .................................................................. 121
Table 134. TMUX_RJ1EXPECTED1_[1
—
32], Expected J1 Byte Value for Port 1 (R/W) ................................... 122
Table 135. TMUX_RJ1EXPECTED2_[1
—
32], Expected J1 Byte Value for Port 2 (R/W) ................................... 122
Table 136. TMUX_RJ1EXPECTED3_[1
—
32], Expected J1 Byte Value for Port 3 (R/W) ................................... 122
Table 137. TMUX_RJ1CAPTURED1_[1
—
32], Captured J1 Value for STS #1 (RO) .......................................... 122
Table 138. TMUX_RJ1CAPTURED2_[1
—
32], Captured J1 Value for STS #2 (RO) .......................................... 122
Table 139. TMUX_RJ1CAPTURED3_[1
—
32], Captured J1 Value for STS #3 (RO) .......................................... 123
Table 140. TMUX_TJ1VALUE_1[1
—
32], J1 Byte Transmit Insert for STS #1 (R/W) ......................................... 123
Table 141. TMUX_TJ1VALUE_2[1
—
32], J1 Byte Transmit Insert for STS #2 (R/W) ......................................... 123
Table 142. TMUX_TJ1VALUE_3[1
—
32], J1 Byte Transmit Insert for STS #3 (R/W) ......................................... 123
Table 143. TMUX Register Map .......................................................................................................................... 124