62
Agere Systems Inc.
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
Register Description
7 Microprocessor Interface and Global Control and Status Registers
Table of Contents
Contents
Page
7 Microprocessor Interface and Global Control and Status Registers ................................................................... 62
7.1 Super Mapper Global Control and Status Registers .................................................................................... 63
7.2 Microprocessor Interface Register Map........................................................................................................ 73
Tables
Page
Table 57. SMPR_VCR, Super Mapper Version Control Register (RO) ................................................................. 63
Table 58. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR (RO) ......................................................... 63
Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO) ..................................................................... 63
Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO) ..................................................................... 63
Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO) ..................................................................... 64
Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO) ..................................................................... 64
Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO) ................................................................... 64
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW) ................................................................... 65
Table 65. SMPR_GTR, Global Trigger Register (RW) .......................................................................................... 66
Table 66. SMPR_MSRR, Block Software Reset Register (RW) ........................................................................... 66
Table 67. SMPR_GCR, Global Control Register (RW) ......................................................................................... 68
Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW) ................................................................ 69
Table 69. SMPR_FCR, Framer Control Register (RW) ......................................................................................... 69
Table 70. SMPR_CLCR, CDR and LVDS Control Register (RW) ......................................................................... 70
Table 71. SMPR_CPCR, Clock and Power Control Register (RW) ...................................................................... 71
Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) ...................................................................... 71
Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW) ....................................................................... 72
Table 74. SMPR_SR, Scratch Register (RW) ....................................................................................................... 72
Table 75. SMPR_TX_LINE_EN1 ........................................................................................................................... 72
Table 76. Microprocessor Interface Register Map ................................................................................................. 73