
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
214
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 252. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)
Table 253. M13_RDL_STATUS, Receive Data-Link Status (RO)
Table 254. M13_RDL_DATA_R, Receive Data-Link Data (RO)
Table 255. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO)
Address
Bit
Name
Function
Reset
Default
000000
0000
0x3F
0x10051
15:6
—
Reserved.
5:0
M13_RFEAC_CODE[5:0]
When the same codeword is received through the FEAC
channel four consecutive times, the M13 will set
M13_RFEAC_CODE[5:0] = x5x4x3x2x1x0, where the
received FEAC codeword is 0x5x4x3x2x1x0 0 11111111,
and it is received right to left.
Address
Bit
Name
Function
Reset
Default
0x000
0
0x10052 15:5
—
Reserved.
This bit is high if the closing flag or an abort byte has been
received.
This bit is high if the frame was ended with an abort byte
rather than a closing flag.
M13_RDL_NOT_BYTE This bit is set if the number of bits in the frame (after removal
of stuffed zeros) is not a multiple of 8.
M13_RDL_OVFL
This bit is set if at least 1 byte of the frame was overwritten by
a byte from a succeeding frame before being read.
M13_RDL_FCS_ERR
This bit is set if the CRC-16 check fails and M13_RDL_FCS =
1 (
Table 287
).
4
M13_RDL_FLAG
3
M13_RDL_ABORT
0
2
0
1
0
0
0
Address
Bit
Name
Function
Reset
Default
0x00
0xXX
0x10053
15:8
7:0
—
Reserved.
M13_RDL_DATA[7:0] Bytes received via the path maintenance data link are stored
in a 128-byte FIFO. They can be read out of the FIFO through
this register, M13_RDL_DATA_R. On reset, the FIFO is emp-
tied, and reading from this register returns an undetermined
value.
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10054
15:7
6:0
—
Reserved.
The number of bytes in the frame modulo-128 is indicated by
this register. This is the number of bytes from the frame that
have been written into the FIFO, not the number of bytes
remaining in the FIFO. All bytes between the opening flag and
the FCS bytes are included (unless M13_RDL_FCS
(
Table 287
) is low, in which case the FCS bytes are included in
the count).
M13_RDL_FRAME_
SIZE[6:0]