TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
38
Agere Systems Inc.
5 Timing Characteristics
(continued)
Table of Contents
(continued)
Tables
Page
Table 38. PSB Interface Receive Timing Characteristics ...................................................................................... 48
Table 39. NSMI (Mode 1) Input Clock Specifications ............................................................................................ 49
Table 40. Input Timing Specifications .................................................................................................................... 49
Table 41. Output Timing Specifications ................................................................................................................. 49
Table 42. SMI (Mode 2) Input Clock Specifications ............................................................................................... 49
Table 43. Input Timing Specifications .................................................................................................................... 50
Table 44. Output Timing Specifications ................................................................................................................. 50
Table 45. Framer Only Mode Clock Specifications ............................................................................................... 51
Table 46. Framer Mode Only Input Timing Specifications ..................................................................................... 52
Table 47. Framer Mode Only Output Timing Specifications .................................................................................. 52
Table 48. Framer
—
LIU Mode Clock Specifications ............................................................................................... 53
Table 49. Framer
—
LIU Mode Input Timing Specifications .................................................................................... 54
Table 50. Framer
—
LIU Mode Output Timing Specifications ................................................................................. 54
Table 51. Microprocessor Interface Synchronous Write Cycle Specifications ...................................................... 55
Table 52. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................... 56
Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................... 58
Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................... 60
Table 55. Input Timing Specifications .................................................................................................................... 60
Table 56. Output Timing Specifications ................................................................................................................. 61