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參數資料

型號：	TMXF84622
英文描述：	TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述：	TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數：	1/62頁
文件大小：	902K
代理商：	TMXF84622

Advance Data Sheet, Rev. 2

July 2001

TMXF84622 155 Mbits/s/622 Mbits/s Interface

SONET/SDH x84/x63 Ultramapper

1 Features

I

Versatile IC supports 622 Mbits/s/155 Mbits/s

SONET/SDH interface solutions for T3/E3, DS2,

T1/E1/J1, and DS0/E0/J0 applications.

I

Implementation supports both linear (1 + 1, unpro-

tected) and ring (UPSR) network topologies.

I

Provides full termination of up to 63 (21 x 3) E1,

84 (28 x 3) T1, or 84 (28 x 3) J1.

I

Low 3.3 V power supply.

I

–40

°

C to +85 °C industrial temperature range.

I

700-pin ball grid array (PBGA) package.

I

Complies with

Telecordia Technologies

*, ITU,

ANSI

, ETSI, and Japanese TTC standards: GR-

253-CORE, GR-499, (ATT) TR-62411, ITU-T

G.707, G.704, G.706, G.783, G.962, G.964,

G.965, Q.542, T1.105, JT-G704, JT-G706, JT-

G707, JT-I431-a, ETS 300 417-1-1, ETS 300 011,

T1.107, T1.404.

SONET/SDH Interface

I

Termination of a single 622 Mbits/s STS-12/STM-4

or single 155 Mbits/s STS-3/STM-1.

I

Built-in clock and data recovery circuit at

622 Mbits/s STS-12/STM-4 interface.

I

Supports overhead processing for all transport and

path overhead bytes.

I

Optional insertion and extraction of overhead bytes

via a serial transport overhead access channel.

Configurable as dedicated DCC channels.

I

Software controlled linear 1 + 1 protection via dedi-

cated interface to protection card.

I

Full path termination and SPE extraction/insertion.

I

SONET/SDH compliant condition and alarm

reporting.

I

Built-in diagnostic loopback modes.

I

8 kHz line frame synchronizing output.

*

Telecordia Technologies

is a trademark of Telecordia Technolo-

gies Inc.

ANSI

is a registered trademark of American National Standards

Institute, Inc.

PDH Interfaces

I

6

DS3, 21 x DS2,

or 6 E3

, 12 x E2.

I

Twenty-one framed or unframed DS1 or E1 inter-

faces.

I

Two additional protection

channels for DS2/DS1/

E1.

STS/STM Pointer Interpreter

I

Interprets STS/AU/TU-3 pointers.

I

Synchronizes 8 kHz frame and 2 kHz superframe

to system-shelf-timing reference by setting the

transmit STS-3/STM-1 pointers to a fixed value

of 522

with an adjustable frame location.

I

Monitors/terminates SPE path overhead.

STS3 Serial Interconnect

I

Serial interface to mate devices.

I

4 Ultramapper devices, 3 configured as mate

devices, provide full termination of an STS-12/

STM-4. A 4 chip solution to terminate

336 DS1s/J1s or 252 E1s.

VT Termination/Generation 84/63 (3x28/21)

I

Supports TIM-V generation and termination for all

84/63 (3x28/21) VT/TU signals.

I

Synchronizes VT/TU SPE to system-shelf-timing

reference by setting the transmit VT/TU pointers to

fixed values for asynchronous mapping or by

dynamically changing the transmit VT/TU pointers

for byte synchronous mapping.

I

Fixed pointer generation in transmit side for asyn-

chronous mapping.

I

Dynamic pointer generation in transmit side for

byte-synchronous mapping.

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相關代理商/技術參數	參數描述
TMXF846221BL-3-DB	制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag
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