參數(shù)資料
型號(hào)： TMXF84622
英文描述： TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述： TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù)： 40/62頁
文件大?。?/td> 902K
代理商： TMXF84622
40
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Symbol
Type
I/O
*
Description
Microprocessor Interface
(continued)
(49)
—
I
21-Bit Address Bus, for 16-Bit Data Bus.
The address bus sig-
nals are latched transparently when ADSN is low.
ADDR20
—
MSB.
ADDR0
—
LSB.
K2, M6, L5,
H1, J2, J3,
G1, L6, H2,
H3, K6, F1,
J5, J6, G2,
E1, F2, H5,
D1, F3, E2
ADDR[20:0]
Note:
The Ultramapper is little-endian, the least significant byte is
stored in the lowest address and the most significant byte is
stored in the highest address. Care must be exercised in
connection to microprocessors that use big-endian byte
ordering.
16-Bit Data Bus.
Device inputs for write operation and outputs for
read operation.
DATA15
—
MSB.
DATA0
—
LSB.
R6, N1, P3,
N2, P5, M1,
P6, M2, L1,
M3, N6, L2,
K1, L3, M5, J1
R5, P2
DATA[15:0]
—
I/O
PAR[1:0]
—
I/O
Data Parity.
Byte-wide parity bits for data. PAR[1] is the parity for
DATA[15:8] and PAR[0] is the parity for DATA[7:0].
Data Transfer Acknowledge.
In synchronous microprocessor
mode, the delay associated with DTN going low depends on the
Ultramapper block being accessed, the address within that block,
and the operating mode. In asynchronous microprocessor mode,
after qualification of ADSN and DSN by TLSC52 clock, DTN going
low depends on the Ultramapper block being accessed, the
address within that block, and the operating mode. Under all con-
ditions the user should wait until DTN is asserted before starting
the next operation. DTN goes high along with the rising edge of
ADSN.
Ultramapper High Priority Interrupt Request (Active-Low).
P1
DTN
—
Open
Drain
O
1
R3
HP_INTN
—
Open
Drain
O
1
Open
Drain
O
1
Open
Drain
O
1
T6
LP_INTN
—
Ultramapper Low Priority Interrupt Request (Active-Low).
R2
APS_INTN
—
Automatic Protection Switch (APS) Interrupt Request
(Active-Low).
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TMXF846221BL-3-DB 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag
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