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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 19/62頁 |
| 文件大小： | 902K |
| 代理商： | TMXF84622 |
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Agere Systems Inc.
19
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
2 The SONET/SDH Ultramapper
(continued)
2.14 Cross Connect Block
The cross connect (XC) is a highly configurable nonblocking crosspoint switch for DS1/E1/DS2 signals, configura-
tion of DS3 signal paths, and configuration of the path overhead access I/O. The cross connect plays a major role
in configuring the interconnection of major function blocks to satisfy an application
’
s implementation.
The cross connect provides the flexibly to tie DS1/E1/DS2 channels from the framer or external pins to the M13
mapper or to the VT mapper. It is also capable of multicast or broadcast operation (one port to many), handling
injected test patterns, idles, or alarm conditions to any channel, and can provide system loopback testing support.
Jitter attenuation may also be inserted in-line on any DS1/E1 channel.
The cross connect can interconnect up to 84 individual DS1/E1 channels between the framer, M13 multiplexer, VT
mapper, jitter attenuator, or external I/O. The external I/O pins support an application dependent mix of up to
29 T1/E1 interfaces (one dedicated protection channel), seven DS2 interfaces, or one of four available framer sys-
tem interfaces.
The cross connect supports an independent signal path for remote alarm indication (RAI), alarm indication signal
(AIS), and byte-synchronous frame synchronizing signals on channels between the VT mapper or M13 and the
framer. Receive pointer adjustment information is routed to the jitter attenuator block for each channel originating in
the VT mapper.
The cross connect has independent DS2 interfaces for the M12 and M23 blocks of the M13 MUX. Full split access
to the external I/O device pins provides the capability to add, drop, or rearrange the DS2 signals within the M13.
For DS3 signals, the cross connect supports configuration of interconnects between the M13 and the SPE, or
external I/O interconnection to the M13 or SPE, or insertion/monitoring of DS3 test patterns from the test-pattern
generator block.
The test-pattern generator block (TPG) provides test signals and monitors inputs (TPM) for signals to and from the
cross connect. The TPG can generate a set of test signals or idles at DS1, E1, DS2, or DS3 rates. There is only
one test pattern generator and monitor per signal rate.
Device pins for the path overhead access channel may be configured to connect to the SPE mapper or TMUX
blocks.
2.15 DS1 Digital Jitter Attenuator
The digital jitter attenuator (DJA) contains 28 copies of the digital jitter attenuator block. These digital jitter attenua-
tor blocks can operate in two different modes, as a DS1 or as an E1 jitter attenuator.
In both modes, the digital jitter attenuator can be provisioned to always operate as a second-order PLL, or it can
switch to a act as a first-order PLL during VT pointer adjustments to help meet MTIE requirements. The period of
time in the first-order mode is provisionable. The PLL bandwidth is provisionable between 0.1 Hz and 0.5 Hz, and
the damping factor for these bandwidths varies between 2 and 0.5 to accommodate a number of different system
constraints.
The block will also insert the proper AIS signal if the primary block AIS control input is active.
2.16 DS3 Digital Jitter Attenuator
The information on the DS3 digital jitter attenuator is not available at this time.
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