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| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 41/62頁 |
| 文件大小： | 902K |
| 代理商： | TMXF84622 |
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Agere Systems Inc.
41
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Pin
Symbol
Type
I/O
*
Description
General Purpose Interface (13)
I
U
Chip Reset (Active-Low).
I/O
D
Performance Monitor Reset.
I
JTAG Test Clock.
This signal provides timing for test opera-
tions.
I
U
JTAG Test Data In.
JTAG test data input signal, sampled on
the rising edge of TCK.
I
U
JTAG Test Mode Select.
Controls test operations. TMS is
sampled on the rising edge of TCK.
I
U
JTAG Test Reset (Active-Low).
This signal provides an
asynchronous reset.
O
JTAG Test Data Out.
JTAG test data output signal is updated
on the falling edge of TCK. The TDO output is 3-stated
except when scanning out test data.
I
U
Disable Output Capability of all Bidirectional and 3-State
Output Buffers (Active-Low).
I
D
(Test Only.) Scan Clock 1.
I
D
(Test Only.) Scan Clock 2.
I
D
(Test Only.) Scan Enable (Active-High).
I
D
(Test Only.) Serial Scan Input for Testing (Active-High).
I
D
(Test Only.) I
DD
Q Input (Active-High).
CDR Interface (7)
I
D
(Test Only.)
Enables functional bypassing of the clock syn-
thesis with a test clock. Active-high.
I
D
(Test Only.)
Controls bypass of 32 PLL-generated phases
with 32 low-speed phases, generated by test logic. Active-
high.
I
D
(Test Only.)
Enables external test control of 155 MHz clock
phase selection through ETOGGLE and EXDNUP inputs.
Active-high.
I
D
(Test Only.)
Moves 155 MHz clock selection one phase per
positive pulse > 20 ns. Active + pulse.
I
D
(Test Only.)
Direction of phase change.
0 = down; 1 = up.
I
D
(Test Only.)
Enables test mode for CDR and PLLs.
I
D
(Test Only.)
Enables CDR test mode shift register.
AP22
AM21
AN22
RSTN
PMRST
TCK
—
—
—
AK21
TDI
—
AP23
TMS
—
AJ21
TRST
—
AN23
TDO
—
AP24
IC3STATEN
—
AM23
AJ22
AN24
AP25
AM24
SCK1
SCK2
SCAN_EN
SCANMODE
I
DD
Q
—
—
—
—
—
AJ15
BYPASS
—
AJ14
TSTPHASE
—
AM15
ECSEL
—
AJ16
ETOGGLE
—
AL17
EXDNUP
—
AK17
AM14
TSTMODE
TSTSFTLD
—
—
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