參數(shù)資料
型號(hào)： TMXF84622
英文描述： TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述： TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁(yè)數(shù)： 27/62頁(yè)
文件大?。?/td> 902K
代理商： TMXF84622
Agere Systems Inc.
27
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
2 The SONET/SDH Ultramapper
(continued)
2.23 HDLC Unit
The HDLC processor formats the HDLC packets for insertion into the programmable channels. A channel can be
any number of bits (1 to 8) from a time slot.
The maximum number of channels is 64. The maximum channel bit rate is 64 kbits/s. The minimum channel bit rate
is 4 kbits/s. Each channel is allocated 128 bytes of storage.
HDLC processing of data on the facility data link (PRMs, Sa bits, or otherwise) is implemented by assigning the
FDL bit position to a logic HDLC channel.
2.24 System Interface and Transport Modes
The system interface block provides a programmable interface. It can be configured to work in the following four dif-
ferent modes:
I
Concentration highway interface (serial time division multiplex interface):
—
Global frame synchronization.
—
Global clock: 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
—
84 transmit and receive data ports; data rates 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or
16.384 Mbits/s
.
I
Parallel system bus (parallel time-division multiplex interface/transmit and receive):
—
Global frame synchronization.
—
Global clock: 19 MHz.
—
Data rate: 19 MHz.
—
8 bits of data + associated parity bit.
—
4 bits of signaling + 2 bits of signaling control + 1 bit of parity.
I
Time-division multiplex data rate serial interface:
—
28 receive frame synchronization (per port).
—
28 receive clock: 1.544 Mbits/s or 2.048 Mbits/s (per port).
—
28 receive ports.
—
One transmit frame synchronization.
—
One transmit clock: 1.544 Mbits/s or 2.048 Mbits/s.
—
28 transmit ports.
I
Network serial multiplexed bus:
—
6- or 8-pin serial interface.
—
Transmit and receive clock and data at 51.84 MHz.
—
Accommodates one DS3 of throughput.
—
Provides a minimal pin count interface for data and inverse multiplexing for ATM (IMA) applications without slip
buffers.
—
Three modes of operation:
Framer
—
NSMI payload assembled/disassembled into DS1/E1s.
M13
—
proprietary transport format with DS3 framing.
SPE
—
proprietary transport format mapped into an STS-1/AU-3.
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