參數(shù)資料
型號： TMXF84622
英文描述： TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述： TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù)： 30/62頁
文件大小： 902K
代理商： TMXF84622
30
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Symbol
Type
I/O
*
TMUX Block
(continued)
STS3/STM1 Mate Interconnect (14)
LVDS
O
155 Mbit/s STS-3/STM-1 Output Data.
LVDS output.
Description
AP17, AP15,
AP13
AP18, AP16,
AP14
AN17, AN15,
AN13
AN18, AN16,
AN14
AK15
AL14
RLSDATAP[3:1]
RLSDATAN[3:1]
TLSDATAP[3:1]
LVDS
I
155 Mbit/s STS-3/STM-1 Input Data.
Input for clock and
Data Recovery (CDR). LVDS input.
TLSDATAN[3:1]
RLSCLK
TLSCLK
—
—
O
O
19.44 MHz Receive Side Byte CLK.
19.44 MHz Transmit Side Byte CLK.
LVDS Control Pins (8)
I
External 100
Resistor Pin 1.
AP3
RESHI
—
Note:
A 100 W 1% resistor is required between RESHI and
RESLO pins as a reference for the LVDS input buffer
termination.
External 100
Resistor Pin 2.
See note in RESHI pin.
External 1 V Reference Voltage Pin.
External 1.4 V Reference Voltage Pin.
LVDS Buffer Terminator Center Tap for RHSDP/N and
RHSCP/N.
Optional, 0.1 μF capacitor connected between
CTAP pin and ground, to improve the common mode rejec-
tion of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for THSCP/N and
THSSYNNP/N.
Optional, 0.1 μF capacitor connected
between CTAP pin and ground, to improve the common
mode rejection of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for RPSDP/N and
RPSCP/N.
Optional, 0.1 μF capacitor connected between
CTAP pin and ground, to improve the common mode rejec-
tion of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for TLSDATAP/N.
Optional, 0.1 μF capacitor connected between CTAP pin and
ground, to improve the common mode rejection of the LVDS
input buffers.
AJ8
AJ6
AK6
AK8
RESLO
REF10
REF14
CTAPRH
—
—
—
—
I
I
I
—
AJ9
CTAPTH
—
—
AK9
CTAPRP
—
—
AJ13
CTAPTL
—
—
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TMXF846221BL-3-DB 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag
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