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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 5/62頁 |
| 文件大小： | 902K |
| 代理商： | TMXF84622 |
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Agere Systems Inc.
5
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
Features
(continued)
I
Capable of detecting/inserting alarm indication sig-
nals (AIS), remote defect indication signals (RDI),
and remote error indication signals (REI).
I
Numerous monitoring functions provided on all the
TUG-3 path overhead bytes.
I
Supports unidirectional path switch ring (UPSR)
applications.
I
N1 tandem connection support is provided.
I
The TUG3 pointer processor can be used for an add/
drop multiplexer.
I
Complies with GR-253-CORE, T1.105, ITU-T G.707,
ITU-T G.831, G.783, ETS 300 417-1-1.
STS12 Pointer Processor Features
I
SONET and SDH compliant.
I
Configurable STS-3/STM-1 or STS-12/STM-4 mode.
I
Supporting an arbitrary mix of STS-1 and STS3c trib-
utaries, and SDH equivalents.
I
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
STS1LT Features
I
Supports standard SPE mappings for sub-STS-1
payloads (VT mapped: 28 DS1, 28 J1, or 21 E1 sig-
nals).
I
Supports standard SPE mappings for STS-1 pay-
loads ( DS3).
I
Detects STS-1 loss-of-signal (LOS) conditions.
I
Detects STS-1 out-of-frame and loss-of-frame (OOF/
LOF) conditions.
I
Provides an 8-bit parallel bus interface for an STS-1
signal.
I
Provides STS-1 selectable scrambler/descrambler
functions and B1/B2/B3 generation/detection.
I
Provides STS-1 pointer interpretation. Detects AIS-P
and LOP
I
Provides STS-1 pointer processing.
I
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.826, G.821, and ETSI 417-1-1.
STS1 XC Features
I
Configurable connection for up to 6 STS1 signals
from 6 SPE mapper transmit blocks to any 1 up to
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the SPE
mapper transmit blocks.
I
Configurable connection for up to 3 STS1 signals
from 3 STS1LT PP blocks to any 1 up to 3 STS1 slots
of any 1 of 4 TMUX transmit interfaces. Clock and
control signals are provided by the TMUX transmit
interfaces and data is supplied by the STS1LT
receive blocks.
I
Configurable connection for up to 12 STS1 signals
from the STS12PP transmit block to any 1 up to
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the
STS12PP transmit blocks.
I
Configurable connection for up to 9 STS1 signals
from 3 CDR receive blocks to any 1 up to 3 STS1
slots of any 1 of 4 TMUX transmit interfaces. Clock
and control signals are provided by the TMUX trans-
mit interfaces and data is supplied by the CDR
receive blocks.
I
Configurable connection for up to 3 STS1 signals
from 6 SPE mapper transmit blocks to any 1 of
3 STS1LT transmit blocks. Clock and control signals
are provided by the STS1LT transmit block and data
is supplied by the SPE mapper transmit block.
I
Configurable connection for up to 3 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 STS1LT transmit
blocks. Data is provided by the TMUX receive inter-
faces for this transfer.
I
Configurable connection for up to 9 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 CDR transmit blocks.
Clock, control signals, and data are provided by the
TMUX receive interfaces for this transfer.
I
Configurable connection for up to 3 STS1 signals
from 3 STS1LT receive blocks to any 1 of 6 SPE
mapper receive blocks. Clock, control signals, and
data are provided by the STS1LT receive block for
this transfer.
I
Configurable connection for up to 6 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 6 SPE mapper receive
blocks. Clock, control signals, and data are provided
by the TMUX receive interfaces for this transfer.
I
Loss of clock detectors on three serial 155 MHz clock
inputs from three CRD RX blocks and one serial
155 MHz clock input from CDR TX block.
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| TMXF846221BL-3-DB | 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag |
| TMXM-0-49 | 制造商:Brady Corporation 功能描述: |
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