參數(shù)資料
型號(hào)： TMXF84622
英文描述： TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述： TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù)： 39/62頁
文件大?。?/td> 902K
代理商： TMXF84622
Agere Systems Inc.
39
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Pin
Symbol
Type
I/O
*
Description
Framer PLL (4)
PLL Clock Input.
Clock generation for Framer 3.3 V PLL.
PLL Control Input for Mode 2/Testmode Output.
PLL Control Input for Mode 0.
PLL Control Input for Mode 1.
Microprocessor Interface (49)
I
Synchronous Microprocessor Clock (when MPMODE = 1).
The maximum clock frequency is 66 MHz. This clock is required
to properly sample address, data, and control signals from the
microprocessor in both asynchronous and synchronous modes
of operation. This clock must be within the range of 16 MHz to
66 MHz.
I
Microprocessor Mode Select.
If the microprocessor interface
is synchronous, MPMODE should be set to 1. If the micropro-
cessor interface is asynchronous, MPMODE should be set to 0.
I
U
Chip Select (Active-Low).
For synchronous mode, it should be
stable beyond a certain setup time before the rising clock edge
when ADSN is active. For asynchronous mode, it should be sta-
ble before DSN is asserted.
I
Address Strobe (Active-Low).
Active-low address strobe that
is a one MPCLK cycle wide pulse for synchronous mode and
active for the entire read/write cycle for asynchronous mode.
Address bus signals, ADDR(20:0), are transparently latched into
Ultramapper when ADSN is low. The address bus should
remain valid for the duration of ADSN.
I
Read/Write Cycle Selection.
RWN is set high for a read opera-
tion, or set low for write operation.
I
Data Strobe (Active-Low).
DSN is not used for synchronous
mode. For asynchronous mode, write operation, DSN becomes
active after data is stable. For read operation, it is similar to
ADSN.
AJ32
AL33
AK30
AG29
AK32
CLKIN_PLL
CG_PLLCLKOUT
MODE2_PLL
MODE0_PLL
MODE1_PLL
—
—
—
—
—
I
D
O
I
D
I
D
I
D
F5
MPCLK
—
F6
MPMODE
—
C1
CSN
—
D2
ADSN
—
H6
RWN
—
E3
DSN
—
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參數(shù)描述
TMXF846221BL-3-DB 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag
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TMXM-1-10-PK 制造商:Brady Corporation 功能描述:MICRO CONSECUTIVE NOS. REPEAT - LEGEND: 1-10
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